ACS Unit for a Viterbi Decoder

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ACS Unit for a Viterbi Decoder

• Garrick Ng, Audelio Serrato, Ichang Wu, Wen-Jiun
  Yong
• Advisor Professor David Parent
• EE166, Spring 2005

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Agenda

• Abstract
• Introduction
• Project Details
• Results
• Cost Analysis
• Conclusions

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Abstract

• Design and implement an 8-bit ACS unit for a
  Viterbi Decoder using Cadence Tools
• Clock speed 90 MHz
• Average Power 3.3 mW
• Area 740 x 320 mm2

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Introduction

• Viterbi Decoder is commonly used in decoding
  convolutional codes for wireless communication
• There are 3 major building blocks
• BMU (branch metric Unit)
• ACS (add-compare-select Unit)
• Survival Path Unit
• ACS unit consumes most power and area

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Project Details

• 8-bit ACS unit operates at 90MHz
• The ACS unit divides into 2 of 8-bit CLAs, one
  8-bit comparator, one 21 multiplexer and DFFs
• The output of the ACS unit is the minimum sum of
  branch metrics and state metrics

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Architecture of ACS Unit
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Longest Path Calculations
ns
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Schematic
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Layout
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Verification
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Testbench of ACS Unit
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Simulations
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Another Test Case
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Output Waveform
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Power
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Cost Analysis

• Estimation of time spent on ACS project
• Research the Viterbi Algorithm (1 week)
• Implementation of the ACS unit (2 weeks)
• Verifying logic (1 week)
• Verifying timing (1 week)
• Layout (2 weeks)
• Post-extracted timing (2 days)

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Lessons Learned

• Use Cell based design
• Great for debugging passing LVS
• Save time in for multiple bits
• Define a manageable scope of project
• To meet project deadline

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Summary

• We designed and implemented an 8-bit ACS unit
  that operates at 90 MHz using 3.3 mW in an area
  of 740 x 320 mm2
• Room for improvement in area and power.

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Acknowledgements

• Thanks to Cadence Design Systems for the VLSI lab
• Thanks to Professor Parent for his time
  guidance