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ITRS Roadmap Design Process Open Discussion EDP 2001

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ITRS Roadmap Design Process Open Discussion EDP 2001 Donald Cottrell Si2, Inc. Technology Trend - The Big Technology Trend - The Bad Technology Trend - The Ugly ... – PowerPoint PPT presentation

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Title: ITRS Roadmap Design Process Open Discussion EDP 2001


1
ITRS RoadmapDesign ProcessOpen DiscussionEDP
2001
  • Donald Cottrell
  • Si2, Inc.

2
Technology Trend - The Big
Designer Productivity
Transistors per Month
Year


3
Technology Trend - The Bad
Mixed Signal

Year
Diversity
4
Technology Trend - The Ugly
  • Mutual Coupling
  • Noise
  • Coupled
  • External
  • Power
  • di/dt
  • IR Drops
  • Electromigration
  • High Frequency
  • Transmission lines
  • Reflections

5
Breaking Down the Walls
Digital
Software
Analog
Architecture
RTL
Synthesis
FloorPlan
Layout
Checking
Mask Prep
Manufacture
6
Breaking Down the Walls
7
EDA Evolution - 2001

8
Reality
  • No external vendor meets all IC design needs,
    All EDA vendors together dont meet all
    needs.
  • Nearly impossible for startups to break into the
    business dueto integration barriers,
  • Startups enter business with intent to be
    purchased, BUT once
    purchased by big guys, a time
    lag and loss of innovation result.
  • Industry partnerships provide value,
    BUT integration acts as a barrier.

9
All or Nothing at All
10
The Need - Customer Choice
11
Customize Solution to Fit the Need
Calibre
SE
Mars-XTalk
12
A Better Model

Open Model and API
4
13
EDA System Needs
Architectural
  • High Performance integration and tools
    Architecture and Assembly Function,
    Performance, Power, .. RTL through Mask design
    and analysis
  • Constraint driven design tools (power,
    timing, signal integrity, )
  • Integration via Open Architecture
    Industry-standard data model
    Industry-standard API
  • Incremental analysis and optimization
  • Concurrent design and analysis
  • Common Calculation Engines
  • Abstracted Model Builders Industry
    Standard interfaces

Architectural
Design
Calculation Engines
Design
Cell and
Core Library
Delay
Delay
Power
RTL
RTL
Function
Extraction
Design
Properties
Design
Cell Geometry
Abstract
Synthesis
Synthesis
Detailed
Process Lib
Floor Plan
Floor Plan
Substrate
Dielectric
Metal
PlaceRoute
PlaceRoute
Via
Incremental
Incremental
Design API
Industry Standard
Extraction
Extraction
Final
Final
Signoff
Signoff
Verification
Verification
Test Generation
Database
14
Standards vs. Innovation
  • Did SQL hurt Relational Database sales?
  • Did MAC grow faster than PC?
  • Are we happy with the rate of university research
    technology transfer?
  • Is there a better way to do cooperative design?
    SoC?
  • Can we continue with ASCII file exchange vs. true
    interoperability?

15
Discussion
  • Do we really need an Open Infrastructure?
  • Will an EDA MicroSoft emerge - Is that bad?
  • Can an EDA Linux model work?
  • Does one-size fit all?
  • Analog/RF/MEMS
  • ASIC (compiled HDL --gt gates)
  • High-volume custom (uP, DSP, embedded memory,
    reprogrammable)
  • SOC (high integration, low cost, low TTM)
  • Memory
  • Are product markets significant?
  • Portable Wireless, Broadband, Internet
    Switching, Mass Storage, Consumer, Computer,
    Automotive
  • Can we develop the necessary metrics?

16
Market Drivers
17
Market Drivers
18
1997 NTRS
19
1999 ITRS
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