FPSLIC European Seminar

1
Monolithic SRAM Based FPSLIC
30 MIPS version available Q4 2001
2
FPSLIC Embedded Blocks

• Software configurable interface between blocks
  already implemented
• Pre-implemented Interface blocks save 2000-5000
  FPGA gates

3
Designer Defined Program and Data SRAM
Allocation

• Memory partition is user defined during
  development
• Easy to trade-off Program and data SRAM

2K Words (x16) for ?FPSLIC (AT94K05)
4
Internal I/O space and Interrupts
Write ldi r16,0x00 ldi r17,0x02 out
FISCR,r16 I/O select 0 out FISUA,r17 r17
data on the bus
02
Data70
I/Oselect0
W
5
Internal Data SRAM Access
True Dual Port Access AVR can disable writing
from FPGA
6
FPSLIC Clocking
7
FPGA Internal Clocking Scheme

• Individual Clock per sector column
• Clock and Clock BAR at sector boundary
• Column Clock can be any one of 8 Global
• clocks
• Clock from Column Clock or Express Bus
• 4 Fast Clocks (2 per side for PCI spec)
• Low power tie-off (lower power!)
• Clock skew lt1ns guaranteed

gtgt Can reduce power by gt50 !
8
FPSLIC Reducing Power consumption
MCU
MEM

• Power is reduced
• by more than 50
• Standby lt100uA
• Active 2-3mA/MHz

Most of power used in I/O pads
ASIC/ FPGA
Monolithic Solution
Discrete Solution
Power is Reduced by 50
9
FPSLIC Resets

• (Internal)
• Watchdog reset AVR only
• FPSLIC Software reset with SFTCR bit

10
FPSLIC - Partial Reconfiguration using AVR
CacheLogicTM

• Hardware implemented for the AVR to control
  partial reconfiguration
• Enable Hardware context switching

11
FPSLIC- CONFIGURATION ( Mode 0)
SRAM
SRAM
AT40K FPGA
AT40K FPGA
Configuration
Reprogrammed
8 Bit RISC MCU
Configurator
2 Wire Protocol

• Automatic download after power up --gt FPGA
  bitstream/AVR code and data/System register
• EEPROM configuration memory can be updated by
  FPSLIC itself
• Extra system parameters can be stored in
  remaining EEPROM

12
Initial AVR-FPSLIC Family

• 5K, 10K and 40K gate AT40K FPGA options
• High performance AVR microcontroller
• 2 UARTs, watch-dog timer, programmable timer,
  interrupt
• Configuration, 2-wire interface, glue logic

13
FPSLIC Applications

• Wireless and Portable systems
• Low power. Stand-by Idd lt 100uA. Active lt100mA.
• Space saving BGA packaging technology
• Reconfigurability (on the fly, remote)
• Secure FPSLIC for sensitive applications

Features

• PDAs and PCMCIA (PCCARD)
• Cell phone accessories
• Digital cameras
• Portable audio
• Smartcard readers
• Wireless security/access systems
• Portable instrumentation
• Medical instrumentation
• Toll Tags
• Irrigation systems/remote monitoring

14
FPSLIC Applications

• Wireline and fixed systems
• High performance 20 MIPS _at_ 25MHz
• Remote updates (reconfigurability)
• Very flexible architecture - platform product
• Space saving BGA packages
• Low power. Stand-by Idd lt 100uA. Active lt100mA
• Secure FPSLIC for sensitive applications

Features

• Home networking / Internet appliance
• Base stations for Wireless systems
• Networking and Telecom line-cards
• Test equipment
• Point of Sale terminals
• Wired security/access systems
• Industrial control and fixed instrumentation
• Image processing systems

15
Atmel Programmable SLi Roadmap
ASIC FPSLICTM /Embeddable FPGA core ASCPs
Available now
AT40K with ARM ARM FPSLICTM
AT40K with RISC uC AVRTM FPSLICTM
AT40KxxAX Low
Features
AT40KxxAV Low
AT40KxxAL Low Avail Now
1.8V 0.12u
1.8V 0.18u
3.3V 0.35u
2000 2001
2002 2003
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FPSLIC System Designer Software Tools
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FPSLIC Design Tools

• Complete IDS7 FPGA Software
• Place route, floorplanning,
• timing analysis, etc.
• Leonardo Spectrum Synthesis Compiler
• VHDL Verilog entry (FPSLIC version)
• ModelSim hardware simulator (FPSLIC version)
• AVR Studio
• Design debugging
• Instruction set simulator
• Assembler

• Co-verification
• PC-based Windows 95/98/NT/ME/2000
• Powered by Mentor Graphics (FPSLIC version)

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FPSLIC Software System Designer
Modelsim for Simulation 10K value Exemplars
Leonardo for Synthesis 10K value Co-verification
powered by Mentor 50K value AVR Studio for
Debug FPGA IDS for Layout
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System Designer?

• Features
• Design Manager
• Environment
• management
• Part Selection Manager
• Co-Verification launcher
• Launch FPGA/uC tools
• Device Dependent
• Methodology Manager
• Controls System Flow
• Bitstream Utilities
• Download Utilities
• Extensive interactive
• help
• Intuitive and easy to
• learn

20
System design without Co-verification
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System design with co-verification
System Designer
Hardware Development
Software Development
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Co-Verification Software
SW Simulation AVR Studio
HDL Simulation ModelSim
Co-Verification Software Backplane
Instruction-Set Simulator
MTI ModelSim Simulator

• Complete Instruction Set
• Interrupt
• Reset
• Instruction Timing

FPSLIC Co-Verification S/W is powered by Mentor
Graphics
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Bitstream Generation
Can generate a complete bitstream (AVR and FPGA)
or can generate an AVR only or FPGA only
bitstream for faster debugging Output file can
be directly downloaded to FPSLIC or used on
industry standard 3rd part programmers
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System Control Register Settings
Everything is programmable in FPSLIC System
Designer gives you control over internal device
settings 64 bits are used for configuring
operating Modes Configuration control Memory
protections and partitioning Dual pin
configuration I/O drive configuration Clock
selection
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System Designer?
ATDS94KSW1 - 995 Annual Subscription or ATDS94
KSW2 - 2495 Purchase Price ATDM94KSW2 - 495
Annual Maintenance
Design Tools