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Timothy O. Dickson and Sorin P. Voinigescu

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Low-Power Circuits for a 2.5-V, 10.7-to-86-Gb/s Serial Transmitter in 130-nm SiGe BiCMOS Timothy O. Dickson and Sorin P. Voinigescu Edward S. Rogers, Sr. Dept of ... – PowerPoint PPT presentation

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Title: Timothy O. Dickson and Sorin P. Voinigescu


1
Low-Power Circuits for a 2.5-V, 10.7-to-86-Gb/s
Serial Transmitter in 130-nm SiGe BiCMOS
  • Timothy O. Dickson and Sorin P. Voinigescu
  • Edward S. Rogers, Sr. Dept of Electrical and
    Computer Engineering
  • University of Toronto
  • CSICS
  • November 15, 2006

2
Outline
  • Motivation
  • High-speed, low-power design techniques
  • 2.5-V, 80-Gb/s BiCMOS Transmitter
  • Measurement results
  • Conclusions

3
Next Generation High-Speed Wireline 100-Gb/s
Ethernet
New design challenges as fundamental frequencies
enter mm-wave regime
4
Power Consumption
should consume less power than
100 Gb/s
10 x 10 Gb/s
State-of-the-art High-Speed Transceivers
Technology 130-nm CMOS SiGe (120-GHz fT)
Data Rate 3.125-to-10.7-Gb/s 2.7-to-43-Gb/s
Integration Single-chip Chip set
Power consumption 800 mW 12 W
Reference Aeluros, ISSCC 2004 Big Bear, ISSCC 2003
5
Power Consumption
should consume less power than
100-Gb/s 41 MUX?
Technology SiGe (210-GHz fT)
Data Rate 132-Gb/s
Supply Voltage -3.3V
Power consumption 1.45 W
Reference IBM, ISSCC 2004
6
MOSFETs vs HBTs
  • HBT _at_ peak-fT VBE 900mV and does not scale!
  • 130-nm nMOS _at_ peak-fT VGS 750mV and
    decreasing!

7
Power reduction techniques
43-GHz latch consumes only 20mW
8
Transmitter Block Diagram
9
2.5-V, 87-Gb/s BiCMOS Selector
86-Gb/s selector consumes 60mW
10
2.5-V, 80-Gb/s BiCMOS Pre-Emphasis Driver
  • MOS gm and input capacitance relatively constant
    as bias current changes.
  • Excellent for output stages with adjustable
    amplitude control.

11
2.5-V, 80-Gb/s BiCMOS Pre-Emphasis Driver
130-nm MOSFETs switching at 80-Gb/s!
12
2.5-V, 80-Gb/s BiCMOS Pre-Emphasis Driver
  • Adjustable pre-emphasis for operation up to
    80-Gb/s
  • Boosts high-frequency content to compensate for
    line losses.
  • Output match S22 lt -10dB up to 94 GHz.

13
36-43 GHz Colpitts VCO
-105 dBc/Hz _at_ 1-MHz offset
  • SiGe HBTs used as negative resistance generators.
  • Differential tuning to reject common-mode noise.
  • Maximize tank swing, bias HBTs at NFMIN for low
    phase noise

14
Die Photograph
PLL
1.5 mm
PRBS 84 MUX
41 MUX Output Driver
1.8 mm
15
Measured Results 80-Gb/s
  • Running for more than 1 hour continuously in the
    lab.
  • Jitter 560 fs (rms) , Rise/fall time 4-5 ps,
    Amplitude 300 mV

16
Verification of Correct Multiplexing
Using pattern capture capabilities of the
Agilent 86100C DCA
17
Verification of Correct Multiplexing
Examine the tone spacing using Agilent E4448A PSA
18
80-Gb/s Amplitude Control
Little degradation in eye quality as amplitude
varies from 100mV to 300 mV per side
19
Maximum Data Rate 87-Gb/s
685 MHz
87 GHz
685 MHz
127
20
Maximum Data Rate vs. Temp.
92-Gb/s _at_ 0oC
71-Gb/s _at_ 100oC
21
Comparison
Technology fT/fMAX Data Rate Supply Voltage Power
130-nm CMOS 85/90 GHz 40-Gb/s (half-rate) 1.5 V 2.7 W
InP HBT 150/150 GHz 43-Gb/s (full-rate) -3.6/ -5.2 V 3.6 W
180-nm SiGe BiCMOS HBT 120/100 GHz 43-Gb/s (half-rate) -3.6 V 1.6 W
180-nm SiGe BiCMOS HBT 120/100 GHz 43-Gb/s (full-rate) -3.6 V 2.3 W
130-nm SiGe BiCMOS MOS 85/90 GHz HBT 150/150 GHz 87-Gb/s (half-rate) 2.5 V 1.36 W
22
Conclusions
  • Described methods for power reduction in
    high-speed building blocks.
  • Use BiCMOS topology to lower supply voltage.
  • Trade off bias current for inductive peaking.
  • Applied these principles to the design of the
    first 87-Gb/s serial transmitter, which consumes
    less power than any 40-Gb/s TX reported to date.
  • As compared with state-of-the-art CMOS, this work
    shows that you can achieve double the data rate
    with half the power dissipation simply by adding
    the SiGe HBT option.

23
Acknowledgements
  • STMicroelectronics Crolles for chip fabrication
  • STMicroelectronics, Gennum, CITO, and NSERC for
    financial support
  • CMC for CAD tools
  • CFI and OIT for equipment and test support

24
Questions?
25
Backups
26
DC Considerations
Need CM resistor in 43-GHz clock buffer
27
Future Directions Futher Power Savings
  • Reduce supply voltage to 1.8V by removing current
    sources.
  • 38 power savings would result in 86-Gb/s TX that
    consumes 825 mW.

28
SiGe Building Block Supply Voltage
DC drops dictate at least 3.3-V supply voltage
150 mV IR
900 mV VBE
900 mV VBE
750 mV VCE
600 mV VCE IR
Unlike CMOS, supply voltage does not scale!!
29
CMOS vs. SiGe BiCMOS
SiGe HBT has 2-generation speed advantage
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