Interra Tech

1

Introduction To Physical Design Flow
2
Technologies

• ICs can also be classified by nature of
  technology or design style used to manufacture
  them. There are three broad technologies/system
  at present.
•  Field Programmable ICs
• PALs, PLDs, FPGAs.
• Semi Custom
• Sea of gates, cell based, CBA., ASICs.
• Full Custom
• Processors, memories, cache, ALU.

3
Design Process Design Representations

• Behavioral Representation
• Describes a circuits function.
• e.g if clock high then counter counter 1.
• e.g out a b c.
• Structural Representation
• It describes the composition of circuits in terms
  of cells and components and interconnects among
  the components. Usually hierarchical.
• Examples are Block Diagrams, Schematic Drawings
  and Netlists of logic gates. It says nothing
  about functionality except what can be inferred
  from the behavior of the components given the
  structure.
• Physical Representation
• It describes the circuit in the information used
  in the manufacturing or fabrication of physical
  systems i.e. design layout.

4
Design Process

• Each Phase of the Design Process is
  typically composed of the following steps

From upper level
Synthesis
From lower level
reject
Analysis
Verification
To upper level
Accept
To lower level
5
Phases of Electronic Design

•  
• Specifications
• Functional Design
• Logic Design
• Circuit and Physical Design

6
Why automate design process ?

•      
• Structured Design Methodology
• Designs should be modular
• Describe the design as formal hierarchy

7
Design Synthesis stages

• Behavioral Synthesis
• Operation of system captured without having to
  specify implementation.
• RTL Synthesis
• Takes an RTL description and convert to registers
  and combinational logic. Automatic programs
  (synthesizer) takes HDL description as input and
  converts to structural description.
• Logic optimization takes description as
  generated by RTL synthesis. Technology mapping
  performed, and technology independent description
  of previous step mapped to standard library.
• Structural to Layout Synthesis
• Optimized network of logic gates and registers
  converted to layout.
• P R , Signal integrity, Crosstalk analysis.

8
Design Verification

• Need for design simulation.
• Simulation types
• Behavioral simulation
• Functional simulation
• Gate-level simulation
• Switch-level simulation
• Transistor-level or circuit-level simulation

9
ASIC Library Generation Flow
SPICE nmos/pmos model
Create Std Cells Schematic
Run Characterization
Adjust W/L of transistor
Performance
No
Met?
Yes
Is DRC LVS Clean?
Yes
Create Layout
Run DRC/LVS
Generate Libraries
Synopsys/LEF/Verilog Models
No
Modify Layout
10
ASIC Design Process
11
Backend Flow Tools

• Design Planning Tool -gt
• Chip Architect ( SYN), LDP (CDN)
• Physical synthesis and Placement -gt
• Physical Compiler, PKS.
• Place and Route-gt
• Apollo, Silicon Ensemble, Plato.
• Signal Integrity-gt
• PrimteTime, Physical Studio.
• Parasitic extraction-gt
• Columbus, StarXT, , Assura, Xcalibre.
• Simulations-gt
• Hspice, Spectre, Tspice.
• Verification - gt
• LVS / DRC Calibre , Diva/ Assura , Hercules.

12
The Problems

• Designs going below 180 nm.
• Interconnect behavior dominating wire is
  increasing.
• Increase in Metal lines , increase in wire pitch.
  
• Coupling capacitance is becoming important.
• High operating frequencies. New metal
  materials ( copper , SiGe )
• Inductance is becoming important.
• Low operating voltages.
• IR drop
• More parasitics causing signal integrity issues.
• Capacitance of clock net increases.

13
Problems a closer look

• Block Level Placement
• Interconnect Driven Floor planning
• High Speed Clock Net Design with Power and Skew
  Constraints
• Floor planning shape generator
• Layout Driven Synthesis
• Placement techniques for large blocks
• RLC Routing
• Variable Accuracy Inductance Extraction
• Coupling Aware Static Timing Enhancements

14
CMOS Process at a glance
15
CMOS Process at a glance
UV light
mask
PR
SiO2
16
Modern CMOS Process - a walk through
17
Modern CMOS Process - a walk through
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Modern CMOS Process - a walk through
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• Thank You