High-Voltage High Slew-Rate Op-Amp Design

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High-Voltage High Slew-Rate Op-Amp Design

• Team Tucson
• Erik Mentze
• Jenny Phillips

Project Advisors Dave Cox Herb Hess
Project Sponsor Apex Microtechnology
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Project Overview
Design a high voltage (/- 200 V) and high slew
rate (1000 V/us) discrete op-amp

• Deliverables
• PCB Prototype
• Amplifier Performance Analysis
• PSPICE Model

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Specific Design Challenges

• Power Limitation (PIV)
• High Voltage required
• Slew Rate I/Cc

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Dr. Jekyll Mr. Hyde

• Circuit theory has a dual character it is a Dr.
  Jekyll Mr. Hyde sort of thing it is two-faced,
  if you please. There are two aspects to this
  subject the physical and the theoretical. The
  physical aspects are represented by Mr. Hyde a
  smooth character who isnt what he seems to be
  and cant be trusted. The mathematical aspects
  are represented by Dr. Jekyll a dependable,
  extremely precise individual who always responds
  according to established custom. Dr. Jekyll is
  the circuit theory that we work with on paper,
  involving only pure elements and only the ones
  specifically included. Mr. Hyde is the circuit
  theory we meet in the laboratory or in the field.
  He is always hiding parasitic elements under his
  jacket and pulling them out to spoil our fun at
  the wrong time. We can learn all about Dr.
  Jekylls orderly habits in a reasonable period,
  but Mr. Hyde will continue to fool and confound
  us until the end of time.
• In order to be able to tackle Mr. Hyde at all, we
  must first become well acquainted with Dr. Jekyll
  and his orderly ways.
• Ernst A. Guillemin
• Taken from the preface to his 1953 book
  Introductory Circuit Theory.

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Project Breakdown

• Dr. Jekyll General Amplifier Topologies
• Find topology candidates
• Throw out those that are obviously deficient
• Analytically compare the finalists to make the
  best choice
• Mr. Hyde Hardware Implementation
• Find components that meet our design requirements
• Adapt chosen topology to meet physical
  requirements
• Simulate Implementation, comparing to Dr.
  Jekylls analytic models
• Implement design, comparing results to simulation
  and analytic models

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Dr. Jekyll
Two Theoretical Techniques to Improve
Slew-Rate 1. Reduce Capacitance - Passive
Frequency Compensation - Active Frequency
Compensation 2. Increase Current -
Non-Saturated Differential Amplifier - Class AB
Push-Pull Gain Stages
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Two Topologies

• Two-Stage Amplifier using Miller Compensation
• Simple Topology
• Uses Passive Frequency Compensation
• Brute Force Solution to Slew-Rate by Driving
  Large Currents into the Compensation Capacitor
• Three-Stage Dual-Path Amplifier
• Complex Topology
• Uses Active Frequency Compensation
• More Elegant Solution to Slew-Rate by
  Significantly Reducing Size of Compensation
  Capacitors, while Maintaining the Ability to
  Drive Large Currents

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Two-Stage Amplifier
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Two-Stage Amplifier

• The real issue at hand here is slew-rate.
• Because the two-stage amplifier (and its higher
  order cousins) use miller capacitors for
  compensation, the pole locations, and as such the
  size of the compensating caps are proportional to
  the ratio of the transconductance.

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Two-Stage Amplifier Governing Equations
Open Loop Gain
Pole Locations
Compensation Capacitor Sizing
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Two-Stage Amplifier Governing Equations
(Continued)
This can be further simplified for comparison if
we cut off the final term under the radical
The Compensation Capacitor is proportional to -
twice the arithmetic mean of the capacitances -
the ratio of transconductances
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Three-Stage Dual-Path Amplifier
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Three-Stage Dual-Path Amplifier

• Uses two Active Compensation techniques
• Damping-Factor Control block
• Removes a compensation capacitor from the output
• Replaces it with an Active-C block that uses a
  significantly smaller capacitor.
• Introduces a high degree of controllability of
  the non-dominate poles.
• Active-Capacitive-Feedback network
• Adds a positive gain stage in series with the
  dominate compensation capacitor, reducing the
  required cap size.
• Gives an enormous amount of flexibility in
  determining the amplifiers dominate poles.

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Three-Stage Dual-Path Amplifier
Because active feedback adds a gain block to each
compensating capacitor, we are able to
simultaneously - reduce capacitance -
increase current drive
The active nature of the feedback allows us to
model the frequency and phase response of the
amplifier according to any frequency response
function we choose.

• A good choice for maximum bandwidth and good
  phase margin is a third-order Butterworth
  response

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Three-Stage Dual-Path Amplifier

• The dimensional values of the active feedback
  transconductance stages and capacitors are set
  according to this response

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Three-Stage Dual-Path Amplifier

• Note that for this amplifier topology the
• slew-rate is going to be defined as

Where Ib and Ia are independently controllable
currents available to charge and discharge the
compensating capacitors.
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Three-Stage Dual-Path Amplifier
This can be further simplified for comparison if
we consider gm3gm5. This is a desirable
performance choice for AB operation in the output
The Compensation Capacitor is proportional to -
the geometric mean of the capacitances - the
root of the ratio of transconductances - a
constant that is less than one
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Performance Comparison
Two-Stage Amplifier
Dual-Path Amplifier
Equal to the product of the geometric mean of
the lumped parasitic capacitances, the root of
the ratio of the transconductances, and a
constant less than one.
Greater than the product of twice the arithmetic
mean of the lumped parasitic capacitances and
the ratio of the transconductances.
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Performance Comparison
We can show that the following is guaranteed
In fact Ca and Cb will be MUCH smaller than Cc!
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Comparison
Three Stage Dual Path
Amplifier
Two Stage Amplifier with
Miller Compensation

1. Simple Topology
2. Reduced Bandwidth
3. Larger Compensating Caps
4. Able to drive large currents to charge and
   discharge caps

1. Complex Topology
2. Extended Bandwidth
3. Smaller Compensating Caps
4. Able to drive large currents to charge and
   discharge caps.
5. Can independently size gain stages that drive
   caps.

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Specific Gain Stages
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Differential Amplifier
Both topologies use a differential amplifier as
the input stage.
As such, a detailed analysis of the available
differential amplifier topologies is needed.
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Source Coupled Diff-Amp

• Source coupled differential pairs are limited to
  sourcing and sinking their biasing current.
• By moving the biasing current source out of the
  signal path this limitation can be overcome.
• Such diff-pair topologies form a class of
  diff-pairs referred to as non-saturating
  differential pairs.

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Nonsaturating Differential Pairs

• Operates the same as a source-coupled diff-pair
  over a given range of differential input values.
• Unlike the source coupled diff-pair however,
  outside of these values the output current does
  not saturate.
• The output current continues to increases
  proportional to the square of the input
  differential voltage.
• This results in a diff-amp that does not exhibit
  slew-rate limitations.

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Source Cross-Coupled Differential Amplifier
Nonsaturated Differential Amplifier
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Source Cross-Coupled Differential Amplifier
Governing Equations
Boundary Conditions for AB Operation
Vbias
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Nonsaturated Differential Amplifier
Governing Equations
ID1
ID2
ISS
ISS
Boundary Conditions for AB Operation
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Summary of Critical Points of Transfer
Characteristics Normalized to Biasing Conditions
Source Cross-Coupled Differential Amplifier
Unsaturated Differential Amplifier
WLOG consider the case where ID2 0
WLOG consider the case where ID2 ISS
This occurs at a differential input voltage of
This occurs at a differential input voltage of
Corresponding to this input is an ID1 value of
Corresponding to this input is an ID1 value of
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Transfer Characteristics
Source Cross-Coupled Differential Amplifier
Normalized to bias conditions
Unsaturated Differential Amplifier
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Output Transfer Characteristics
Normalized to bias conditions
Source Coupled Diff-Pair
Source Cross-Coupled Differential Amplifier
Unsaturated Differential Amplifier
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Comparison of Source Cross-Coupled Diff-Pairs
Source Cross-Coupled Differential Amplifier
Nonsaturated Differential Amplifier
Large Step Transconductance becomes
approximately equal for a large enough input step.
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THE BIG QUESTION!
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Which one has the most useful advantages???
?
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?
?
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Class AB Amplifier

• Combines high-gain common source amplifier with a
  unity gain source follower
• No output slew-rate limitations
• Output voltage swing limited to a threshold below
  VDD and above VSS

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Current Limiting on AB Output

• IOUTMIN VTHP/R
• IOUTMAX VTHN/R
• Gate drive is removed from M1 or M2 if current
  leaves range

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Mr. Hyde
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Specific Design Challenges

• Power Limitation (PIV)
• High Voltage required
• Slew Rate I/Cc

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Physical Implementation Challenges

• Must bias devices within specifications
• Power limitation means biasing devices so minimal
  voltage drop across each
• Allow maximum current through devices

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Devices Found

• TO92 Package
• Zetex ZVN0545A
• Zetex ZVP0545A
• Surface Mount
• Zetex ZVP0545G
• Zetex ZVP0545G

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TO92 Specifications
N-Channel P-Channel
Drain-Source Voltage 450 V -450 V
Continuous Drain Current 90mA -45 mA
Pulsed Drain Current 600 mA 400 mA
Power Dissipation 700 mW 700 mW
Gate-Source Voltage /- 20 V /- 20 V
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Surface Mount Specifications
N-Channel P-Channel
Drain-Source Voltage 450 V -450 V
Continuous Drain Current 140 mA -75 mA
Pulsed Drain Current 600 mA -400 mA
Power Dissipation 2 W 2 W
Gate-Source Voltage /- 20 V /- 20 V
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Device Models

• Have working PSPICE models for devices
• BSIM3v3 models
• Verified with IDS v. VDS plots

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Cost of Devices

• NMOS (TO92)
• 10 Parts for 20.70
• 100 Parts for 124.20
• 500 Parts for 483.00
• PMOS (TO92)
• 10 Parts for 23.22
• 100 Parts for 139.32
• 500 Parts for 541.80

• NMOS (Surface Mount)
• 10 Parts for 11.25
• 100 Parts for 67.50
• 500 Parts for 262.50
• PMOS (Surface Mount)
• 10 Parts for 13.55
• 100 Parts for 81.27
• 500 Parts for 316.05

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PCB

• Sierra Proto Express
• PCB Express
• Advanced Circuits

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Project Schedule

• Finalize Amplifier Topology 11/19/04
• Preliminary Simulation Results 1/17/05
• Final Simulation Results 1/28/05
• Perfboard Testing Completed 2/11/05
• PCB Layout Finalized 2/18/05
• Preliminary Modeling 3/4/05
• Write Test Procedures 3/11/05
• PCB Test and Measurement 3/19/05
• Final Modeling 3/25/05
• Tie up Loose Ends by EXPO! 4/29/05

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Q A
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References

• 1 H. Lee, et al., A Dual-Path Bandwidth
  Extension Amplifier Topology With Dual-Loop
  Parallel Compensation, IEEE J. Solid-State
  Circuits, vol. 38, no. 10, Oct. 2003.
• 2 H.T. Ng, et al., A Multistage Amplifier
  Technique with Embedded Frequency Compensation,
  IEEE J. Solid-State Circuits, vol. 34, no 3,
  March 1999.
• 3 H. Lee, et al., Active-Feedback
  Frequency-Compensation Technique for Low-Power
  Multistage Amplifiers, IEEE J. Solid-State
  Circuits, vol. 38, no 3, March 2003.
• 4 K. Leung, et al., Three-Stage Large
  Capacitive Load Amplifier with Damping-Factor-Cont
  rol Frequency Compensation, IEEE Transactions on
  Solid-State Circuits, vol. 35, no 2, February
  2000.
• 5 H. Lee, et al., Advances in Active-Feedback
  Frequency Compensation with Power Optimization
  and Transient Improvement, IEEE Transactions on
  Circuits and Systems, vol. 51, no 9, September
  2004.
• 6 B. Lee, et al., A High Slew-Rate CMOS
  Amplifier for Analog Signal Processing, IEEE J.
  Solid-State Circuits, vol. 25, no. 3, June 1990.
• 7 E. Seevinck, et al., A Versatile CMOS
  Linear Transconductor/Square-Law Function
  Circuit, IEEE J. Solid-State Circuits, vol.
  SC-22, no. 3, June 1987.
• 8 J. Baker, et al., CMOS Circuit Design,
  Layout, and Simulation. New York, NY John Wiley
  Sons, Inc., 1998.
• 9 B. Razavi, Design of Analog CMOS Integrated
  Circuits. Boston, MA McGraw Hill, 2001.
• 10 Sedra, Smith, Microelectronic Circuits, 5th
  ed. New York, NY Oxford University Press, 2004.