An Overview of a 20Msps 12bit Pipelined ADC

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An Overview of a 20Msps 12bit Pipelined ADC

• Dr. Chris Hutchens
• SSC San Diego
• Oklahoma State University

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Outline
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Outline Cont
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Introduction/Motivation
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ADC Specification Review
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ADC Specification Review
Line fit of the x-fer function
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ADC Specification Review
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Ideal Flash Error
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Pipeline Overview
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Pipelined Stage Conversion
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Error Correction
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Error Correction
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Error Correction
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Error Correction (Cont)
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Residual Voltage Errors
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T/H Topology and Noise
Flip Around
Charge Redistribution
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Auto-Zero MDAC Schematic
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MDAC Noise
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Flash ADC
Offset must be reduced by 5 or 6 to ensure yield.
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Two Phase Timing
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Two Phase Timing
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Amplifier Requirements
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Amplifier Requirements
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Amplifier Summary
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Amplifier Summary
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Amplifier Summary
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Amplifier Summary
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Amplifier Summary
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Amplifier Summary
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Amplifier Summary
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Comparator
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Boosted Switches
Conceptual Bias Scheme
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Issues remaining Areas
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Individual Focus Areas
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Immediate Pending Tasks