Digital Signal Processing Basics and AO Back-Ends - PowerPoint PPT Presentation

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Digital Signal Processing Basics and AO Back-Ends

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Title: Digital Signal Processing Basics and AO Back-Ends


1
Digital Signal Processing Basics and AO Back-Ends
  • Luis A. Quintero
  • Digital Section Head
  • Electronics Department
  • Arecibo Observatory

2
Introduction to Digital Signal Processing
3
Continuous Signal Acquisition - Transducers
4
Sampling
Continuous-time Signal (real signal)
Amplitude
time
5
Signal Storage in Computers
time
6
Analog to Digital Converter Quantization
time
7
Analog to Digital Converter Quantization
time
2
5
2
1
4
4
6
http//www.iusb.edu/

8
Digital Signal Processing System
Computer
A/D
D/A


Analog-to-Digital Converter
Digital-to-Analog Converter
Computer (Digital System) - Micro Processor
- DSP (MAC) - Logic Circuit - ASIC -
PAL/CPLD - FPGA
Data Storage Data Processing - Math
Operations - Filters - Fourier Transform
- Data Format
9
Sampling Rate Analog to Digital
Fs 9 samples/second 9Hz
Fs 19 samples/second 19Hz
Better signal reconstruction More computer memory
/ BW and
10
Analog to Digital Converter - Clock Input
ANALOG
DIGITAL
A/D

Clock for digital circuit
Stable jitter
11
Resolution
Resolution 3bits, 23 8 combinations
7
Values from 0 to 7
0
Resolution 4bits, 24 16 combinations
15
Values from 0 to 15
time
0
Better signal quantization More computer memory
and
12
Saturation
  • Resolution 3bits, 23 8 combinations
  • Too much power to the ADC
  • Saturation caused by interference (RFI)

13
Sampling FT, Nyquist and Aliasing
14
Sampling FT, Nyquist and Aliasing
Fs 200Hz, Ts 5ms, Fs/2 100Hz
15
Signal Processing Adder
4bit adder
4
5

4
1bit adder
16
Signal Processing Multiplier
4
8
4
  • Multiplication by a Constant Gain
  • Multiplication by -1, Sign change
  • Multiplication by a function e.g. sin/cos -
    up/down conv.
  • Things to consider
  • Bit growing
  • Precision Approximation Errors

17
Signal Processing Functions, e.g. sin/cos
xn
xn sinn
sinn
DDS
18
Signal Processing Synchronization
19
Filtering e.g. Finite Impulse Response (FIR)
20
Auto Correlation
21
Discrete Fourier Transform - DFT
Xk FNxn
FFT Fast Fourier Transform, optimized DFT
(butterflies)
22
Examples with Signals
  • Fourier Transform
  • Saturation
  • Averaging
  • Clock Jitter

23
Fourier Transform, one tone
24
Fourier Transform, two tones
25
Fourier Transform, noise effect
26
Fourier Transform, averaging
27
Fourier Transform, longer transf.
28
Fourier Transform, Saturation
29
Fourier Transform, Clock Jitter
0 Jitter
40 Jitter
30
Applications in Radio Astronomy
31
Gregorian Dome Receivers
Ganesan, R. Telescope Electronics, May 2006
32
Radio Frequency Signal Path
33
Signal Transport Intermediate Freq.
34
Final Stage Data Acquisition
Data Sampling and Storage
35
Bandpass Signals in IF
36
Sampling - Nyquist Zones Analog BW
37
Wideband Arecibo Pulsar Processor (WAPP)
  • 4 WAPPs
  • 1 WAPP 2 IF Channels
  • 2 Correlators
  • 1 Multiplexer
  • 50/100 MHz BW
  • auto / crosscorrelations
  • Step attenuators
  • Technical issues
  • Difficult to troubleshoot
  • Obsolete parts

38
Wideband Arecibo Pulsar Processor (WAPP)
39
WAPP Correlators (1995)
High Performance CMOS Correlator Chip (ASIC)
  • 16 Chips per board
  • Autocorrelation / Crosscorrelation
  • 1024 Lags / chip
  • 100MSPS each
  • Low Power
  • TTL compatible

http//www.naic.edu/astro/general_info/correlator
/cmos.html
40
Complex Sampling
41
Arecibo L-band Feed Array
  • 7 Receivers
  • Dual Polarization
  • 14 analog signals
  • 1225 1525MHz
  • 300MHz BW
  • Designed by Germán Cortés Medellín (Cornell)

Ganesan, R. Telescope Electronics, May 2006
42
Complex Sampling Example ALFA
1225
1525
43
Mock Spectrometer / PDEV (2007)
  • Designed and developed by Jeff Mock
  • 8 x AD9430, 12bits ADCs
  • 2 x Xilinx Virtex II Pro FPGA
  • 2 QDR Mem, 2M x 36
  • 1x PowerPC Processor
  • Flash SRAM mems
  • 2 x GbE, 2 x RS232
  • 5 x SMA (clk, PPS, etc)
  • LCD 128x64 pixels

Digitizers
Digital Board
44
PDEV Architecture
QDR 2Mx36
Flash / SRAM
PCIe x8 MGT
ADC
GX 2VP70
ADC
ADC
ADC
2 x GbE
PPC 440GX
2 x RS232
ADC
GX 2VP70
ADC
ADC
ADC
4 x SMA
PCIe x8 MGT
QDR 2Mx36
45
PDEV Mock Spectrometer
TEST SIGNAL
CW, Noise, CW Noise
12
ADC0
12
ADC0
SWITCH
PROC. INT.
STOKES
ACCUMULATOR
PACKETIZE
GAIN/OFFSET
PFB/FFT 16-8k
DDC (DDS, LPF)
12
ADC0
12
ADC0
CONFIGURATION REGISTERS
46
EALFA / PALFA Backend
14 PDEVs 7 for 7 ALFA pixels (primary) 7
for 7 ALFA pixels (commensal) 14 File servers
(4TB) We own in total 24 PDEVs DDC (DDS, Mixer,
DLPF) PFB (up to 8192 channels) Stokes
parameters Accumulation, Packing
http//www.naic.edu/phil/talks/vc09/tel_Perf_da
tatking_09.ppt
47
GALFA Spectrometer / GALSPECT (2004)
  • Backend for the
  • Arecibo L-band Feed Array (ALFA) multibeam
    receiver
  • 7 beams, dual polarization
  • Outputs
  • Narrowband 8192channels,
  • 7MHz BW
  • Wideband 512 channels,
  • 100MHz BW

48
PR Ultimate Pulsar Processing Instrument ( PUPPI)
  • 100/200/400/800MHz BW
  • Polyphase Filter Bank
  • Dual Pol. 8 bit ADC
  • Full Stokes
  • 200MB per second recording (10GbE)
  • 0-15.5dB Level Control
  • PSRFITS data format
  • 1xBee2 2xiBOB

49
Recording Systems Mark IV / 5A / 5C / RDBE
  • Mark IV Mark 5A 1Gbps (125MB every second)
  • RDBE Mark5C 4Gbps (500MB every second)
  • eVLBI, AO-UPR-Centenial link 155Mbps all
    time512Mbps 24h-6h

50
Roach Radar Backend RRB
  • Complex Baseband - Digital Down Converter (DDC)
  • 50MHz bandwidth max.
  • 2 x IF channels (polA/polB)
  • Bit selection, 8/4bits
  • 1.6Gbps max. data rate
  • Doppler correction
  • Programmable digital filter
  • Hardware (three systems)ROACH Signal
    Proc.katADC 2x1.5Gsps_at_8bitRAID Server, dual
    10GbE
  • Fixed parameters Summer 2012

51
Analog v.s. Digital
52
Down Conversion
53
Digital Down Conversion
54
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