Microprocessor-based systems Course 2

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Microprocessor-based systemsCourse 2

• General structure of a computer

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Components of a computer system

• Classic computer model (J. von Neumann)
• Control unit (CU)
• Arithmetical and logical unit (ALU)
• Memory (M)
• Input device(s) (ID)
• Output device(s) (OD)

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Components of a computer system

• Microprocessor-based computer system a
  bus-based system

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The Central Processing Unit (CPU)

• Control Unit (CU)
• Responsible for
• Instruction fetch (read)
• Instruction decoding (interpretation)
• Generation of command signals needed to execute
  the instruction
• It is a sequential circuit (state automatom)
• The Arithmetical and Logical Unit (ALU)
• Executes arithmetical and logical operations
• Arithmetic ,-,/,, modulo, comparisons
• Logic SI, SAU, NU,
• Shifts and rotations
• Usually it is a combinational circuit
• Registers
• General purpose registers (GR)
• Holds data
• Take part in arithmetic and logic operations
• Special purpose registers ()
• Addressing registers
• Status register

CPU
CU
CG
RI
PhG
ID CCB
PC
SR
ALU
GR

R1
Rn
R2
System Bus
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Control Unit (CU)

• The brain of the computer
• It is composed of
• Clock generator (CG)
• Generates the clock (synchronization) signal
• Phase generator (PhG)
• Generates the phases needed for instruction
  execution
• The Instruction Decoder (ID) and the Command and
  Control Block (CCB)
• Interpret the instructions and generate command
  signals needed for instruction execution
• Instruction register IR
• Keeps the current instruction
• Program counter PC
• Keeps the address of the next instruction (to be
  executed)
• (Program) Status Register (SR)

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Arithmetical and Logical Unit

• Ac Accumulator register
• Keeps one of the operands and the result
• R register for the 2nd operand
• SR Status register

n
n
R
Ac
n
n
Operation
ALU
n
SR
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Arithmetical and Logical Unit

• One bit adder with carry
• Si Ai Bi Ti-1
• Ci AiBi Ci-1(Ai Bi)

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n bits adder
Bn-1
An-1
B1
A1
B0
A0
?n-1
?1
?0
Cn-1
Cn-2
C1
C0
C-1
Sn-1
S1
S0
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Adding operation with 2 registers
Step Operation Commands
1 Clear A Transfer D ? B (operand 1) Ad 0, CLKA ? (impuls) CLKB ?
2 Transfer B ? A , D ? B (operand 2) Ad 1, CLKA ?, CLKB ?
3 A ? A B Ad 1, CLKA ?
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Circuit for adding and subtraction in 2th
complement

• For adding Ad/Sub 0
• For subtraction the second operand is
  complemented
• Ad/Sub1

D0
D1
Dn-1
CLKB
B0
B1
Bn-1
Ad / Sub
Tn-1
?0
?1
?n-1
T1
T0
CLKA
A0
A1
A n-1
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Logical unit with 4 operations
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Multiply operation
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Implementation of the multiply operation
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Multiply algorithm

• Write the operands into the registers B ? X, Q ?
  Y, clear the accumulator A ? 0
• Complement the operands if they are negative
• Test Q0
• Q0 0, shift A and Q to the right
• Q0 1, add A B A and shift A and Q to the
  right
• Repeat step 3 until Yn-1 get into Q0. In the
  last step the shift is not necessary
• AS BS QS
• Complement the result if AS 1

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Division circuit
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Division algorithm

• Load the first operand in registers A and Q
• Load the second operand in register B
• Memorize AS BS in QS. If
• AS 1, complement A, Q
• BS 1, complement B
• Tests
• A B, overflow
• B 0, division by 0
• A 0 and Q lt B, result 0
• Shift A, Q to the left and put 0 in Q0
• Subtract B from A and put the result in A. If
• AS 0, shift left A, Q and put 1 in Q0
• AS 1, add B to A, shift left A, Q and put 0 în
  Q0
• 6. Repeat step 5 for n times
• 7. Round the result if A B, add 1 to Q
• 8. If QS 1 complement register Q

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Adding in floating point representation

• Load the operands into registers
• Compare the exponents (5 cases)
• ex ey, add mantissas and copy the exponent
• ex gt ey and (ex ey) lt mantissas bits, than my
  is aligned by shifting to the rights with ex-ey
  positions and than add mx with my
• ex gtgt ey and (ex ey) mantissas bits, than
  copy X into the result
• ex lt ey si (ey ex) lt mantissas bits, than
  mantisa mx is aligned by shifting to the rights
  with ey-ex positions and than add mx with my
• ex ltlt ey si (ey ex) mantissas bits, than
  copy Y into the result
• 3. Normalize the result. Test the bits around the
  decimal point and if necessary shift the mantissa
  to the right or to the left and increment or
  decrement the exponent

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Adder circuit for floating point numbers
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Multiply and division in floating point
representation

• Multiply is made as follows
• add the exponents
• multiply the mantissas
• normalize the result
• Division is made as follows
• subtract exponents
• divide mantissas
• normalize the result

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Design of a simple computer

• Design steps
• 1. Establish the destination and the domain of
  use for the computer
• 2? Define the instruction set and instruction
  format
• 3? Design the block scheme of the central
  processing unit
• 4? Decompose instructions into micro-operations
  and phases
• 5? Define the logical equations/functions for the
  micro-comands
• 6? Design the logical scheme for the PhG and CCB
• 7? design the other modules IR, PC, GR, ALU, SR,
  CG
• 8? Design of memory modules
• 9? Design of I/O interfaces
• 10? Optimize the scheme through steps 2-9

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Simple computerDesign steps

• Destination
• General purpose computer
• Special destination computers
• embedded computers
• signal processing computers
• control systems
• High performance computers
• Parallel and distributed systems (GRID, Cloud,
  etc.)
• Instruction set
• Instruction format (length and fields)
• Fixed
• Variable
• Operation Types
• Arithmetic
• Logic
• Transfer
• Jump and branch
• Stack operations, etc.

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Instruction format
Operation codes 0 0 0 1 1 0 1 1
7 6
5 0
7 6 5 4 3 2 1 0


Address field
Op. code
0 0 0 0 0 1 . . . 1 1 1

• Instructions
• JMP
• ADD
• MEM

• NOP
• CLA
• CPL
• SHL
• SHR
• SKIPO
• SKIPN
• STOP

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Scheme of a simple computer