Timing Analysis

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Timing Analysis

• Section 2.4.2

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Delay Time

• Def Time required for output signal Y to change
  due to change in input signal X
• Up to now, we have assumed this delay time has
  been 0 seconds.

t0
t0
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Delay Time

• In a real circuit, it will take tp seconds for
  Y to change due to X

t0
ttp
tp is known as the propagation delay time
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Timing Diagram

• We use a timing diagram to graphically represent
  this delay

Horizontal axis time axis Vertical axis
Logical level axis (Logic One or Logic Zero)
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Timing Diagram

• We see a change in X at t0 causes a change in Y
  at ttp

Horizontal axis time axis Vertical axis
Logical level axis (Logic One or Logic Zero)
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Timing Diagram

• We also see a change in X at tT causes another
  change in Y at tTtp

We see that logic circuit F causes a delay of tp
seconds in the signal
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Simple Example Not Gate
Let tp2 ns Where ns nanosecond 1x10-9
seconds
2ns
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Simple Example 2 Not Gates
Let tp2 ns
4ns
2ns
2ns
Total Delay 2ns 2ns 4ns
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Simple Example 2 Not Gates
Notes Time axis is shared among signals
Logic levels (1 or 0) are implied, not shown
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Simple Example 2 Not Gates
Sometimes dashed vertical lines are added to aid
reading diagram
2ns
2ns
2ns
2ns
2ns
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Where does this delay come from?

• Circuit Delay

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Circuit Delay

• All electrical circuits have intrinsic resistance
  (R) and capacitance (C).

Lets analyze a simple RC circuit
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Circuit Delay Simple RC Circuit
Vin
Vout
Note
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Circuit Delay Example
Vin
Vout
Let R1ohm, C1F, so that RC1 second Time
Delay is 0.7s or 700 ms for 0.5Vdd Time Delay is
2.3s for 0.9Vdd Time Delay is 4.6s for 0.99 Vdd
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How do we relate this to logic diagrams?
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Def tplh
tplh low-to-high propagation delay time
This is the time required for the
output to rise from 0V to ½ VDD
tplh
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Def tphl
Tphl high-to-low propagation delay time
This is the time required for the
output to fall from Vdd to ½ VDD
tphl
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Def tp (propagation delay time)
Lets define tp propagation delay time as
This will be the average delay through the
circuit
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Gate Delay Simple RC Model
Ideal gate with tp0 delay
RC network
Tptp_not
Equivalent model with Gate delay of tp_not
Ideal gate with RC network
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Gate Delay - Example
X
0
25ns
5ns
Y
tp_not
0
5ns
30ns
We indicate tp on the gate
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Combinational Logic Delay
Longest delay
This circuit has multiple delay paths A-Y
5ns5ns5ns15ns B-Y 5ns5ns5ns5ns20ns C-Y
5ns5ns5ns15ns D-Y 5ns
Shortest delay
Longest delay 20ns Shortest delay 5ns
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Combinational Logic Delay
Longest delay
Well use the longest delay to represent the
logic function F. Lets call it Tcl for time,
combinational logic
Shortest delay
Longest delay 20ns
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Combinational Logic (CL) Cloud Model
Tcl20ns
Tcl20ns
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Logic Simulators

• Used to simulate the output response of a logic
  circuit.

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Logic Simulations

• Three primary types
• Circuit simulator (e.g. PSPICE)
• Exact delay for each gate
• Most accurate timing analysis
• Very slow compared to other types
• Functional Simulation (e.g. Quartus )
• Assumes one unit delay for each gate
• Very fast compared to other types
• Most inaccurate timing analysis
• Timing Simulation (e.g. Quartus)
• Assumes average tp delay for each gate
• Not the fastest or slowest timing analysis
• Provides pretty good timing analysis

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TPS Quizzes
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Timing Quiz 1
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Calculate all delay paths through the circuit
shown below
What is the shortest and longest delay?
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Solution Calculate all delay paths through the
circuit shown below
This circuit has multiple delay paths A-Y
5ns5ns10ns20ns B-Y 2ns5ns5ns10ns22ns B-Y
8ns5ns10ns23ns C-Y 8ns5ns10ns23ns D-Y
10ns
Shortest path10ns Longest path23ns
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Timing Quiz 2
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Given the circuit below, find(a) Expression for
the logic function(b) Longest delay in original
circuit
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Solution Given the circuit below, find(a)
Original logic function(b) Longest delay in
original circuit
Longest Delay 7ns7ns 14ns
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Timing Quiz 3
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Given the circuit below,(a) Using Boolean
Algebra, minimize the logic function(b) Longest
delay in minimized circuit Delay times are
NOT gates 2ns AND,OR gates 5ns NAND,
NOR gates 7ns XOR gates 10ns XNOR
gates 12ns
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Solution Given the circuit below, find(a)
Minimized logic function(b) Longest delay in
minimized circuit Delay times are NOT
gates 2ns AND,OR gates 5ns NAND, NOR
gates 7ns XOR gates 10ns XNOR gates
12ns
You can show
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Solution Given the circuit below, find(a)
Minimized logic function(b) Longest delay in
minimized circuit Delay times are NOT
gates 2ns AND,OR gates 5ns NAND, NOR
gates 7ns XOR gates 10ns XNOR gates
12ns
Longest delay is 7ns
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Solution Expanded
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Given the circuit below,(a) Using a Truth Table
and a K-map, minimize the logic function
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Solution

• Do yourself!

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D-FF Timing

• Section 6.3.3

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Def Clock Period and Switching Frequency
Tc
0
Tc cycle period, seconds
Switching frequency,
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D-FF Timing Parameters
time
Timing Diagram
0
Tsu setup time D must be stable
(unchanging) tsu seconds before the clock
edge Thd hold time D must be stable
thd seconds after the clock edge. Tq
register delay time Q becomes valid tq
seconds after the clock edge.
If Tsu or Thd are violated, data are NOT stored
in D-FF
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Maximum Switching Frequency

• How fast can our circuits operate

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Maximum Switching Frequency Model
No feedback and thd0ns
W
We need to find the minimum time, Tc,min, needed
to propagate a signal from input X to node W.
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Maximum Switching Frequency Model
No feedback and thd0ns
W
From the model, we see that the minimum cycle
time is
Register Setup time
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Timing Diagram Maximum Switching Frequency
This model assumes tqtout lt tintcltsu
Tc,min
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Clock is too fast!!!
We have a setup time violation because the clock
is too fast!!!
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Correcting a Setup Time Violation

1. Slow down the clock so that

However, in most cases, Tc is a system parameter
which cannot be changed. Plus, most users want
their designs to go faster not slower.
2. Use a pipeline design. Lets examine this
option more closely.
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Original Design
W
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Pipeline Design
Lets break the F Logic into two components, so
that F F1 F2 and tcl tcl1
tcl2
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Pipeline Design
Now, lets add two register blocks. One between
F1 and F2 and another one at the output.
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Pipeline Design Minimum Cycle Time for Each Stage
Stage 1
Stage 2
Stage 1
Stage 2
For simplicity,
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Pipeline Design Maximum Switching Frequency
Calculation
Stage 1
Stage 2
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Pipeline Design Maximum Switching Frequency
Calculation
We have,
where

so,
or,
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Pipeline Design Maximum Switching Frequency
Calculation
Stage 1
Stage 2
In other words, the pipeline design can run 2x
as fast as the original design. Lets look at a
timing diagram to see why.
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Stages 1 and 2 run in parallel
Too Slow
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End of Lecture
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N-stage Pipeline Design
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Lets extend this concept to an N stage
pipe What is the maximum switching frequency?
Let the total logic delay Tcl Tcl1Tcl2 .
Tcl,N
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i.e. all stages have equal delays.
We have for each stage
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Now, assume
So
Or,
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In other words, the pipelined design will
operate N times faster than the original design.
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Now, lets set
So
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constant
So,
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In other words, the absolute maximum frequency of
any design is fixed at
We can use this formula to perform a back of the
envelope calculation to determine if a desired
switching frequency is feasible
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• The pipeline approach is a very powerful design
  technique.
• However, we have two major trade-offs using a
• pipelined design. They are
• Data Load Time and 2. Data Latency Time
  

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DATA Load Time
At power-up, we must first load the pipeline.
This will require a time of
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DATA Latency Time
Data will require a finite time to progress
through the pipe, this is equivalent to the Data
load time.
unacceptable
Note as,
we find,