OpAmp (OTA) Design

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OpAmp (OTA) Design

• The design process involves two distinct
  activities
• Architecture Design
• Find an architecture already available and adapt
  it to present requirements
• Create a new architecture that can meet
  requirements
• Component Design
• Design transistor sizes
• Design compensation network

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All op amps used as feedback amplifier
If not compensated well, closed-loop can be
oscillatory or unstable.
damping ratio z phase margin PM / 100
Value of z 1 0.7 0.6 0.5 0.4
0.3 Overshoot 0 5 10 16 25 37
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UGF frequency at which gain 1 or 0 dB
PM phase margin how much the phase is
above critical (-180o) at UGF
Closed-loop is unstable if PM lt 0
UGF
PM
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Two Stage Op Amp Architecture
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z
7
UGF
GMlt0
p1
p2
z1
PMlt0
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UGF
p1
p2
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UGF
GM
p1
p2
z1
PM
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Types of Compensation

• Miller - Use of a capacitor feeding back around a
  high-gain, inverting stage.
• Miller capacitor only
• Miller capacitor with an unity-gain buffer to
  block the forward path through the compensation
  capacitor. Can eliminate the RHP zero.
• Miller with a nulling resistor. Similar to Miller
  but with an added series resistance to gain
  control over the RHP zero.
• Self compensating - Load capacitor compensates
  the op amp (later).
• Feedforward - Bypassing a positive gain amplifier
  resulting in phase lead. Gain can be less than
  unity.

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General Miller effect
v2
v1
i
v2 AVv1
v1
i v1/Z1
i
i (v1-v2)/Zf v1(1-AV)/Zf - v2(1-1/AV)/Zf
i -v2/Z2
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Miller compensator capacitor CC
C1 and CM are parasitic capacitances
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DC gain of first stage
AV1 -gm1/(gds2gds4)-2 gm1/(I5(l2 l4))
DC gain of second stage
AV2 -gm6/(gds6gds7)- gm6/(I6(l6 l7))
Total DC gain
gm1gm6
AV
(gds2gds4)(gds6gds7)
2gm1gm6
AV
I5I6 (l2 l4)(l6 l7)
GBW gm1/CC
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Zf 1/s(CCCgd6) 1/sCC
When considering p1 (low freq), can ignore CL
(including parasitics at vo)
Therefore, AV6 -gm6/(gds6gds7)
Z1eq 1/sCC(1 gm6/(gds6gds7))
C1eqCC(1 gm6/(gds6gds7))CCgm6/(gds6gds7)
-p1 w1 (gds2gds4)/(C1C1eq)
(gds2gds4)/(C1CCgm6/(gds6gds7))
(gds2gds4)(gds6gds7)/(CCgm6)
Note w1 decreases with increasing CC
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At frequencies much higher than w1, gds2 and gds4
can be viewed as open.
Total go at vo
CC
gds6gds7gm6
CCC1
vo
Total C at vo
C1CC
CL
CCC1
-p2w2
CCgm6(C1CC)(gds6gds7)
CL(C1CC)CCC1
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gds6gds7
Note that when CC0, w2
CL
As CC is increased, w2 increases also.
However, when CC is large, w2 does not increase
as much with CC. w2 has a upper limit given by
gm6gds6gds7
gm6

CLC1
CLC1
When CCC1, w2 (½gm6gds6gds7)/(CL½C1)
Hence, once CC is large, its main effect is to
lower w1, and hence lower GBW.
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Also note that, in contrast to single stage
amplifiers for which increasing CL improves PM,
for the two stage amplifier increasing CL
actually reduces w2 and reduces PM.
Hence, needs to design for max CL
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There are two RHP zeros
z1 due to CC and M6
z1 gm6/(CCCgd6) gm6/CC
z2 due to Cgd2 and M2
z2 gm2/Cgd2 gtgt z1
z1 significantly affects achievable GBW.
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gm6/(CLC1) f (I6)
A0
z1 gm6/Cgd6
w2
w1
z2 gm2/Cgd2
-90
No PM
-180
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gm6/(CLC1) f (I6)
A0
z1 gm6/Cgd6
z2 gm2/Cgd2
w2
w1
z1 gm6/Cc
-90
No PM
-180
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gm6/(CLC1) f (I6)
A0
w2
z1 gm6/CC
w1
gm1/CC
-90
PM
-180
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It is easy to see
PM 90o tan-1(UGF/w2) tan-1(UGF/z1)
To have sufficient PM, need UGF lt w2
and UGF ltlt z1
In such case, UGF GB
gm1/CC z1 gm1/gm6.
GB lt w2 GB ltlt z1
Hence, need
PM requirement decides how much lower
PM 90o tan-1(GB/w2) tan-1(GB/z1)
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Possible design steps for max GB

• For a given CL and Itot
• Assume a current share ratio q, i.e.
• I6I5 Itot, I5 qI6 , I1 I2 I5/2
• Size W6, L6 to achieve max gm6/(CLCgs6) which is
  gt w2
• C1 ? W6L6, gm6 ? (W6/L6)0.5
• Size W1, L1 so that gm1 0.1gm6
• this make z1 10GBW
• Select CC to achieve required PM
• by making gm1/CC lt 0.5 w2
• Check slew rate SR I5/CC
• Size M5, M7, M3/4 for current ratio, IMCR, etc

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Comment

• If we run the same total current Itot through a
  single stage common source amplifier made of M6
  and M7
• Single pole go/CL
• Gain gm6/go
• Single stage amp GB gm6/CL gtgm6/(CLC1)
• gt w2 gt gm1/CC GB of two stage amp
• Two stage amp achieves higher gain but speed is
  much slower!
• Can the single stage speed be recovered?

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Other considerations

• Output slew rate SR I5/CC
• Output swing range VSSVdssat7 to VDD Vdssat6
• Min ICM VSS Vdssat5 VTN Von1
• Max ICM VDD - VTP - Von3 VTN
• Mirror node approx. pole/zero cancellation
• Closed-loop pole stuck near by
• Can cause slow settling

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When vin is short, the D1 node sees a capacitance
CM and a conductance of gm3 through the diode
con. So p3 -gm3/CM
When vin is float and vo0. gm4 generate a
current in id4id2id1. So the total conductance
at D1 is gm3 gm4. So z3 -(gm3gm4)/CM 2p3
If p3 ltlt GB, one closed-loop pole stuck nearby,
causing slow settling!
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Eliminating RHP Zero at gm6/CC
icc vg gm6 CCdvCC/dt
vg RZCCdvCC/dt vcc
CCdvCC/dt
(gm6RZ-1)CCdvCC/dt gm6vcc0
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For the zero at M6 and CC, it becomes
z1 gm6/CC(1-gm6Rz)
So, if Rz 1/gm6, z1 ? ?
For such Rz, its effect on the p1 node can be
ignored so p1 remains as before.
Similarly, p2 does not change very much.
?similar design approach.
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Realization of Rz
vb
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Another choice of Rz is to make z1 cancel w2
z1gm6/CC(1-gm6Rz) - gm6/(CLC1)
CCCLC1
? Rz
gm6CC
CLC1
1
(1 )

CC
gm6
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Let ID8 aID6, size M6 and M8 so that VSG6
VSG8
Then VSGzVSG9
Assume Mz in triode
Rz bz(VSGz VT - VSDz) bz(VSGz
VT) bz(2ID8/b9)0.5
bz(2aID6/b6)0.5(b6/b9)0.5 bz/b6 b6VON6
(ab6/b9)0.5 bz/b6 1/gm6(ab6/b9)0.5
Hence need bz/b6 (ab6/b9)0.5 (CCCLC1)/CC
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gm6/(CLC1) f (I6)
A0
-z1
w2
w1
gm1/CC
-90
PM
-180
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• With the same CC as before
• Z1 cancels p2
• P3, z3, z2, not affected
• P1 not affected much
• Phase margin drop due to p2 and z1 nearly removed
  
• Overall phase margin greatly improved
• Effects of other poles and zero become more
  important
• Can we reduce CC and improve GB?

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A0
gm6/CL
Operate not on this but on this or this
z1 p2
z2 gm2/Cgd2
z4 gm6/Cgd6
w2
w1
-90
-180
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Increasing GB by using smaller CC

• It is possible to reduce CC to increase GB if
  z1/p2 pole zero cancellation is achieved
• Can extend to gm6/CL
• Or even a little bit higher
• But cannot push up too much higher
• Other poles, zeros
• Imprecise mirror pole/zero cancellation
• P2/z1 cancellation
• GB cannot be too high relative to these p/z
  cancellation
• Z2, z4, and pz-1/RZCC must be much higher than GB

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Possible design steps for max GB

• For a given CL and Itot
• Assume a current share ratio q, i.e.
• I6I5 Itot, I5 qI6 , I1 I2 I5/2
• Size W6, L6 to achieve max single stage GB1
  gm6/(CLCoutpara)
• Make z4gm6/Cgd6 gt (1050)GB1
• Choose GB aGB1,
• Choose CC to make p2 GB/(1020)
• Size W1, L1 and adjust q so that gm1/CC GB
• Make z2gm2/Cgd2 gt (1020)GB
• Size Mz so that z1 cancels p2
• Make sure pz due to Mz and CC gtgt GB
• Make sure PM at fGB is sufficient
• Size M3/4 so that gm3/CM is gt GB/(1020)
• Check slew rate, and size other transistors for
  ICMR, OSR, etc

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Simple transistor circuits

• Can use any of ideal current or voltage
  sources, resisters, and switches
• Use one or two transistors
• Examine various ways to place the input and
  output nodes
• Find optimal connections for
• high gain
• high bandwidth
• high or low output impedance
• low input referred noise

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Single transistor configurations

• Its a four terminal device
• Three choices of input node
• For each input choice, there are two choices for
  the output node
• The other two terminals can be at VDD, GND,
  virtual short (V source), virtual open (I
  source), input, or output node
• Most connections are non-operative or duplicates
• D and S symmetric B not useful

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2 valid input choice and 1 output choice
Connection of other terminals
or
Resister
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Capacitor
Gnd or virtual
Common source
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This is D
To VDD
Source follower
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N-channel common gate
p-channel common gate
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Diode connections
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Building realistic circuits from simple
connections
flip vertical ?
Combine ?
N common source
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flip left-right ?
N common source
Combine to form differential pair ?
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Vbb
flip upside down to get current source load ?
Vbb
?Combine to form differential amp
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Can also use self biasing and convert to single
ended output ?
Replace virtual gnd by current source?
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two transistor connections

• Start with one T connections, and add a second T
• Many possibilities
• many useless
• some obtainable by flip and combine from one T
  connections
• some new two T connections
• Search for ones with special properties
• in terms of AV, BW, ro, ri, etc

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First MOST is CS
D1 connects to D2 (with appropriate n-p pairing)
-kvo
vo
vin
CS with negative gm at output node
CS
Push pull CS
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When Vx gnd T2 is not useful
When Vx Vin, T2 and T1 are just one T
Vo
When Vx -kVo what do we get?
Vx
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Vxgnd, M2 is I source
Vx vin, ?
Vo
Vx - vin, ?
M1
M2
Vx vo, capacitor
Vx
Vx kvo, negative gds feedback
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M4
M3
vo
-vo
M1
M2
-vin
vin
gm1
M5
AV
gm1vingds1vo gds3vo-kvogm30
gds1gds3-kgm3
gds1gds3
AV ? when k
gm3
GBWgm1/Co GBW of simple CS
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D1 connects to S2
Cascode
just a single NMOST
any benefits?
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Vo
-kVx
-kVo
Vx
Cascode with positive Vx feedback
Cascode with positive Vo feedback
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Vin
Vo
Vo
Vo
Effects on GBW?
Folded cascode
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Vx
-kVo
-Vx
Vo
Vo
folded cascode with positive feedback
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flip up-down for source?
connecting D1 to S2 ?cascoding
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flip left-right to get this differential telescopi
c cascoded amplifier?
add M9 to change gnd to virtual gnd?
GBWgm1/Co
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How to connect G3 to Vx, kVx, or kVo
Same GBW Gain can be very high
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How to connect G3 to Vx, kVx, or kVo
Same GBW Gain can be very high
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flip up-down for I sources?
connecting n-D to p-S
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folded cascode amp
Same GBW
Vbb
Vin
Vin-
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How to connect for positive feedback?
Vbb
Vin
Vin-
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D1 connects to G2, two stages
two stage CS amplifier
CS amplifier with a source follower buffer
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• Needs compensation and CM feedback
• Can gain be higher than single stage?
• Can GBW be improved vs single stage?

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Vx
-vin
-Vx
Can you connect without loading effect?
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Vomin Vin-min Vdssat or VT 3Vdssat
Biasing?
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But is the gain improved? Is GBW improved?
Vomin 2Vdssat
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?V?
Vx
Vx
Same as above, only T2 is pMOS
Connecting S1 to D2 makes ro really small ?buffer
or output stage
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or
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?
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connecting S1 to G2
Vx
Vx
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Vx
?
Vx?
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connecting S1 to S2
Vo
Vo
-Vin
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connecting S1 to D2
V?
V?
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?
?
e.g. ?
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M1 is common gateD1 connects to G2
Vin
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D1 connects to S2
Vin
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PSRR
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Vout AddVdd Av(V1-V2) AddVdd - AvVout
? Vout(1Av) AddVdd
Good as long as Av gtgt 1, or f lt GB
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• DC gain ignore all caps and find relationship
  between vdd and vout
• at vout? Dgm1 at Id1?same at Id2?Dgm1/(gds2gds4)
  at G6?vg6gm6/gds6 across DS6 ?vdd
  Dgm1/(gds2gds4) gm6/gds6
• Vdd/vout gm6gm1/gds6(gds2gds4)

For zeros, set vdd 0, vout float. This is the
unity gain buffer configuration of the
amp. Hence, char roots are -GB and p2
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For poles, make vout 0, vdd float. Three nodes
S3/S4/S6, G3/G4/D1 ignore Write KCL at D2/D4/G6
node v(gds2gds4sCIsCC)vdd(gds4gds11) Curren
t balance in M6 gm6(v-vdd)gds6vdd
?v(1gds6/gm6)vdd gds6/gm6(gds2gds4)(1gds6/gm
6)s(CIsCC)0
gds6/gm6(gds2gds4)
-s(CIsCC)
Pole at - gds6(gds2gds4) /(gm6(CCCI))
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Similar computation for PSRR-

1. Get DC gain
2. Get zeros they are the same as in PSRR, and the
   same as poles of unity feedback Avd
3. Get dominant pole

Practice this, and see if you get similar results
as in book
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• Two-Stage Cascode Architecture
• Why Cascode Op Amps?
• Control the frequency behavior
• Increase PSRR
• Simplifies design
• Where is the Cascode Technique Applied?
• First stage -
• Good noise performance
• Requires level translation to second stage
• Requires Miller compensation
• Second stage -
• Self compensating
• Reduces the efficiency of the Miller compensation
• Increases PSRR