Lab 15 :BCD Counters and Frequency Division:

1
Lab 15 BCD Counters and Frequency Division
BCD Numbers.
Slide 2
MOD 100 BCD Counter..
Slide 3
Slide 4
Frequency Division
Slide 5
Frequency Division and the UP-1 board.
2
Lab 15 BCD Numbers
A BCD number is a Binary Coded Decimal number. It
is a 4 bit code used to represent the decimal
numerals 0, 9. The 4 bit numbers above 9 are
not used in this number system.
Converting decimal to BCD Example convert 25 to
BCD Convert each decimal numeral to BCD.
5
2
0010
0101
Thus 25 00100101BCD
Converting BCD to decimal Example convert
0110010111BCD to decimal.Start at the BCD point
and group BCD bits into blocks of four. Convert
each block into a BCD number.
0110010111
7
9
1
Thus 0110010111BCD 197
Slide 2
3
Lab 15 Mod 100 BCD Counter
A MOD 100 BCD counter is made up of two 4count
symbols. Each 4count symbol is a MOD 10 counter.
Here is the first Mod 10 counter.
1
0
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
0 0 0 0
0 0 0 0
0 0 0 1
1 0 0 0
1 0 0 1
1 0 1 0
0 0 0 0
1
0
1
0
1
The NAND gate will output a 1 when the count is 0
to 9.
The NAND gate will output a 0 when the feedback
condition 10 is reached. This will re-start the
counter at 0.
Add a second MOD 10 counter.
Connect the clocks together.
Connecting COUT and CIN will not work. COUT of
the first counter is 1 when the counter reaches
15. At 15 the first counter signals the CIN of
the second counter to count up by one on the next
clock pulse. 15 is the terminal count which is
never reached by a MOD 10 counter. An AND gate
connected to CIN of the second stage is required.
The inputs of the AND gate connects to QA and QD
of the first counter. QA and QD are 1 when the
counter is 9. This is the terminal count for a
MOD 10 counter.
Start the count at 0.
Both NAND gates are 1 and the AND gate is 0 when
the count is 0 to 8. The first counter counts the
second counter holds 0 because CIN0. Skip ahead
in the count to 8.
At 9 the AND gate outputs a 1 to CIN.
The next clock pulse will create the feedback
condition for the first counter. CIN 1 for the
second counter means the its count goes to 1.
Slide 3
This cycle repeats itself at 19, 29 The counter
counts from 0 to 99 in BCD
4
Lab 15 Frequency Division
Frequency of a pulse waveform is its pulse rate.
A counter halves the frequency of the input clock
at each of its outputs.
Slide 4
5
Lab 15 Frequency Division and the UP-1 board
The UP-1 board has a 25,1275,000 PPS oscillator.
Connecting a counter to a set of LEDs and
clocking the counter at this fast rate would
result in a count that would not be
distinguishable on the LEDS. All LEDs would
appear to be on at the same time.
Connecting the UP-1 oscillator to a 24 stage
counter will divide the frequency down to a rate
that is distinguishable on LEDs. Grouping any 4
adjacent outputs creates a MOD 16 counter. Each
MOD 16 counter group counts a slower speed.
Pulse rates must be less than 30 PPS in order to
be distinguishable on LEDs.
Slide 5