Design Techniques for High-Resolution Current-Mode Sigma-Delta Modulators

1
Design Techniques for High-Resolution
Current-Mode Sigma-Delta Modulators
2
Outlines

• Introduction
• Current-Memory Modulator Architecture
• Current-Memory Cell Design
• Modulator Architecture
• Chip Architecture
• Experimental Results
• Conclusion

3
Introduction

• Current Memory
• Compatible with Digital Technology
• Obstacles Noise, Gain Error, Nonlinearity
• Nonlinearity
• Presence of Out-of-band Noise with Large
  Amplitudes in the Modulator
• Mash 2-1 Modulator Architecture
• Stability While Providing Higher Order Noise
  Shaping

4
Elementary Two-Input Current-Memory Cell

• The Sum of Input Current during Acquisition Phase
• The Memorized Current at the Output during
  Restoration Phase
• Output Current gt Inverted Sum of the Input
  Current

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First-Order and Second-Order Noise-Shaped
Modulator
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Some Different Noise-Shaped Transfer Function
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A Second-Order MASH modulator
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A Current-Memory Implementation of the MASH 2-1
Architecture
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Comments for MASH 2-1 Architecture

• Using Two Phase Integrator
• Advantage
• 50 Increase in the clock speed
• Reduction of the Noise Power, Gain Error,
  Nonlinearity, and Settling Error
• Stability

10
Typical Current-Memory Cell Design
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Typical Current Memory Cell Design (Cont.)

• Main Problems
• Early Effect
• Vg2 is a nonlinear function of the Iin2.
• Vg2 and Sw12 make the drain voltage of Mm1 a
  nonlinear function of the output current of
  cell1.
• Settling Error on Vg2
• Charge Injection on Cg2

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Typical Current Memory Cell Design (Cont.)

• Main Solutions
• Two-Step Approach
• Common Gate Stage
• High Output Impedance
• Long Settling Times to Minimize Contribution
• Large Capacitance (100pF, 37pF)

13
Final Current-Memory Cell Design
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Modified Current-Memory MASH 2-1 Modulator
Architecture
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Pseudodifferential Modulator Configuration
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Measured Output Power-Spectrum for fs640kHz and
an Input Amplitude-10 dB
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Measured Total SNDR for fs640kHz
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Summary of Measured Results