ECE 345 Senior Design Project

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ECE 345 Senior Design Project

• High Efficiency Class D Amplifier (Group 12)
• TA Inseop Lee
• Presented by Brian Shields Yau N. Wong

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What is Class D Amplifier ?
Block Diagram

• Characteristics
• Driving switching drivers with complementary PWM
  signals
• Output - no direct path to ground at all time
• Very high power efficiency

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Why Class D Amplifier ?

• Very High Efficiency Output Stage ( gt 75 )
• High Fidelity can be Achieved ? Low Total
  Harmonics Distortion

• Applications
• Hearing Aids
• Most of the portable applications that run on
  batteries

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Overall Design Objective

• Power Efficiency - 75 or Greater
• Fidelity - THD of 1 or Less

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PWM Generator
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Audio Preamplifier (LM387)
Block Diagram

• Advantages
• Low Noise ? Improve the overall noise
  performance of the amplifier
• Internally compensated ? less component counts

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Triangle Wave Generator

• Requirements
• highly linear ? quality of modulation
• frequency 200KHz or greater
• Several Designs Proposed
• Integration of Square Wave
• Charge and Dump
• LM566 - Voltage Controlled Oscillator

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Integration of Square Wave
Block Diagram
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Integration of Square Wave
Simulation Results

• Disadvantage
• Non-stable DC offset and irregular pulse shape

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Charge and Dump
Block Diagram
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Charge and Dump
Simulation Results

• Disadvantage
• faster pulse generator needed (555 tried) - 100ns

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LM566 - Voltage Controlled Oscillator
(Final Design)

• Problem
• 6V DC Bias at output
• Solution
• DC Blocking Capacitor - 0.68uF used

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Comparator - LM311 !?
Block Diagram
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Comparator - LM311 !?
Simulation Results

• Simulations worked fine with LM311
• Didnt work on board ? testing ? too SLOW !

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Comparator - LM360
Block Diagram

• Fast enough ? 20ns max.
• Simple ? No external components required

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Output Stages
GOALS

• Using the Pulse Width Modulated signal as the
  gate input to MOS drivers, deliver power to the
  speaker.
• Using a simple low pass filter (LPF), remove the
  carrier frequency at 200 kHz.

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Delay Circuit
PURPOSE

• To ensure maximum efficiency, all the power at
  the output stage should be delivered across the
  speaker.
• We need to produce two signals, one for PMOS and
  one for NMOS, which ensure both are never on at
  the same time.

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Delay Circuit
SIGNALS NEEDED
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Delay Circuit
SIGNAL PRODUCTION
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Delay Circuit
SIGNAL PRODUCTION (cont.)
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Delay Circuit
OVERALL LOGIC DESIGN
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Delay Circuit
PSPICE OUTPUT
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Delay Circuit
DELAY ELEMENT IN CIRCUIT
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Delay Circuit
PSPICE OUTPUT
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TTL Signal Amplifier
DS0026

• Purpose
• The TTL output waveforms (3 - 4 volts) are not
  guaranteed to turn on MOS devices.
• Description
• High speed two-phase clock driver and interface
  circuit between TTL logic and MOS logic levels.
• Benefits
• 20ns rise/fall times
• High output current drive (1.5 A)

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MOS Drivers LPF
Logic Design
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Low Pass Filter
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Blocking Capacitor
Problem and Solution

• Solution Use two 4700 uF capacitors
• ( 9400 uF) to block signal.

Z .0033 Ohm
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Efficiency Calculations
Efficiency 0.06125 W / 0.0718 W Efficiency
85.31
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Testing - Total Harmonic Distortion
(THD)
Block Diagram of Testing Setup
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Testing - Total Harmonic Distortion
(THD)

• Results
• Highest THD 0.127 at 20KHz
• Lowest THD 0.036 at 2KHz

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Conclusion
Class D Amplifier
Goals Total Harmonic Distortion lt 1 Efficiency
gt 75
Results Total Harmonic Distortion lt .127
Efficiency 85.31