An Ion-Trap Microarchitecture for Quantum Computation

1
An Ion-Trap Microarchitecture for Quantum
Computation

• Tzvetan S. Metodi, Darshan D. Thaker, and
  Frederic T. Chong
• University of California

Andrew W. Cross and Isaac L. Chuang Massachusetts
Institute of Technology
2
The Quantum Architecture Research Center
John Kubiatowitz
Isaac Chuang
Fred T. Chong
Mark Oskin
3
Quantum Computers Today
FACTORING (NMR)
QARC
NMR
01
Supercond
.
Ion Trap
01, LANL
00
00, LANL
99, Oxford
03
Complexity ( gates)
00
04, NIST
98
01, NIST
99,01
03
99,00, MIT
00
Ion trap DJ
99
00, Frankfurt
00
00, NIST
02,
NIST /
Saclay
98
98, LANL
99, Oxford
Delft / UK
99, Cambridge
00, NEC
03, NEC
96, NIST
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2
3
4
5
6
7
of quantum bits
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Our Goal
Factor 2048-bit Number
107 gates
106 gates
Factor 1024-bit Number
106 qubits
105 qubits
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Building a Quantum Architecture

• Reliable and Realistic Technology
• Reliable initialization
• Universal set of quantum operations
• Ability to Measure the system
• Fault-Tolerant Structures and Error Correction
• Efficient Quantum Resource Distributions.

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Brief Talk Outline

• The Ion-Trap Technology
• Quantum Logic Array (QLA) overview
• Communication Mechanism
• Example (FT Toffoli Gate)
• Numerical Results and Conclusion

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Trapped Ions for Quantum Computation
aluminum substrate
laser
Cirac and Zoller in 95. A number of atomic ions
trapped in a linear RF trap that interact with
Lasers beams to quantum compute.
ion (Be)
electrode
segmented RF Paul Traps
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Single-Trap Example
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Trapped Ions for Quantum Computation
aluminum substrate
laser
Cirac and Zoller in 95. A number of atomic ions
trapped in a linear RF trap that interact with
Lasers beams to quantum compute.
ion (Be)
electrode
segmented RF Paul Traps
Lasers implement logic gates and measurement,
where multi-qubit gates are implemented using the
vibrational modes of multiple ions coupled in a
linear chain.
Sympathetic Recooling ions are needed to reduce
the vibrational heating, which affects the gate
fidelity
cooling laser
data ion
Mg
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QCCD Quantum Charge Coupled Device
our abstraction
Original QCCD

• Array of Linear Traps allow scalability by
• limiting the number of ions per trap.
• Quantum communication via
• ballistic transport from the memory
• region to the interaction region. Ions
• are moved by changing trapping voltages.

Kielpinski et al, Nature v417, p 709, 2002
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Error-Correction Example
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Quantum Logic Array (QLA) a reconfigurable
microarchitecture
Basic Building Block
Data Ions
Electrodes
Cooling Ions
Quantum Channels

• QLA design trades area for communication to
  provide both scalability and flexibility for
  large-scale fault-tolerant architectures
• Basic Blocks Each building block consists of
  electrodes, the data ion, the sympathetic cooling
  ion, and free space around it to allow for the
  building of channels when the basic blocks are
  tiled together.
• Fault-Tolerant Structures Large-scale
  fault-tolerant architectures can be built by
  tiling basic blocks to form logical qubits and
  interconnect channels between them. Qubit
  structures are built at design-time with
  computations mapped at run-time.

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High Level Architecture Overview
Average physical gate failure rates are assumed
to be 10-7 with cell size of 20 by 20 microns.
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High Level Architecture
Classical Control Processors
Logical Qubit
Logical Qubit
720 µm
49 Physical Ions --- 5292 trap cells
R
R
R
Classical Control Processors
Logical Qubit
Logical Qubit
Logical Qubit
2940
R
R
R
2.11 mm2
100 logical qubits per 90nm-technology Pentium 4
processor, compared to 55 million classical
transistors within each such P4
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Inter-Qubit Communication
destination
source
Qk
EPR
Q1
256 qubits 30,000 cells

• Ballistic channels are too faulty for the data
  to move through at very large distances.
• We use the concept of teleportation developed by
  Bennet et. al. in 93, which employs entangled EPR
  pairs to recreate the state of an ion at the
  desired destination without physically moving the
  ion.
• The EPR pairs are purified upon arrival with the
  use of ancillary EPR pairs, which are constantly
  reinitialized to zero.

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Quantum Repeaters
EPR pair
Qk
Q1
R
R
source
destination
R
R
R
R
R
R
R
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Quantum Repeaters
EPR pair
Qk
Q1
R
R
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Quantum Repeaters
EPR pair
Qk
Q1
R
R
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Quantum Repeaters
EPR pair
Qk
Q1
R
R
Teleporting the data
Next Channel Detail
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Communication Channel Detail
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Communication Channel Detail
Total Communication Distance (cells)
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Simple Example Toffoli Gate
X
X
Discovered by Toffoli in 1981, the Toffoli Gate
is a controlled-controlled-NOT gate. This gate is
a universal gate for reversible computation and
is a special case for the three bit universal
gate for quantum logic.
Y
Y
Z
Z
xor XY
The NAND gate is contained within the Toffoli
X
X
Toffoli
Y
Y
1
X nand Y
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Fault-Tolerant Toffoli Gate Construction
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Simple Example (FT Toffoli Gate)

• Heuristic Greedy Scheduler that grabs all
  available bandwidth whenever it can.
• Goal is to find the minimum number of paths and
  bandwidth between logical qubits such that
  communication and computation can be overlapped.

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FT Toffoli Scheduler
Move A2 --gt C2
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FT Toffoli Scheduler
Move C2 --gt A1 Move A2 --gt C1
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FT Toffoli (Numerical Estimations)
3 ancilla preparations data interaction 316
5 53 ECC cycles. At 0.043 seconds per ECC
cycle at level 2, we have 2.5 seconds per
Toffoli gate.
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Factoring an Integer (RSA)
Classical Factoring Exponential complexity.
Cavallar in 2000 has demonstrated the
factorization of a 512-bit number in seven
calendar months on 300 fast workstations, two SGI
Origin 2000 computers, and one Cray C916
Supercomputer - a process which amounts to 8400
MIPS years. Quantum Factoring Shors Algorithm
proposes polynomial time, however real time
estimates currently dont exist due to the
complexity of the system.
QFT
Classical Post processing
Modular Exponentiation
Period of
f(x)
Toffoli
Toffoli
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Factoring an Integer
QFT
Classical Post processing
Modular Exponentiation
Period of
f(x)

• 128-bit 63,730 Toffoli Gates with 21 ECC steps
  per Toffoli for modular exponentiation. Thus we
  have 21(63,730)QFT 1.34 x 106 time steps
  16 hours. ? 161/.75 ? 21 hours
• 512-bit 397.910 Toffoli Gates QFT ? 5.5 days
• 1024-bit 964,919 Toffoli Gates QFT ? 13.4
  days
• 2048-bit 2,301,767 Toffoli Gates QFT ? 32
  days

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Multi-Chip Area Solution
Single Chip
D1
D2
Q
Q
Q
Q
BS
To Next Chip
Q
Q
Optical Fiber

Imaging Lens
Q
Q
Q
Q
Laser Beams
ION
Two ion-trap chips are connected through an
optical fiber network, where collected photons
into a Beam Splitter (BS) station from two remote
ions are measured forcing the ions into an
entangled state. After the entanglement procedure
we can teleport data ions from one chip to the
next.
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Laser Limitations

• Current lasers are the size of room!
• Expect 6-12 lasers
• Distribute with MEMS mirror

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MEMS Mirror Array
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SIMD Control

• Many mirrors but few lasers -gt similar to Single
  Instruction Multiple Data computers
• Limits to parallelism -gt longer computation -gt
  more error correction -gt more control (!)

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Future Work

• Scheduler to optimize execution time and number
  of lasers
• Compiler to minimize data lifetimes
• Traditionally, maximal parallelism minimizes data
  lifetimes implicitly by minimizing execution time
• Goal explicitly minimize data lifetime and
  reduce parallelism to reduce machine size

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Future Work (2)

• Decoherence-Free Subspaces
• Error correction assumes uncorrelated errors
• Pair ions and use difference to represent data -gt
  cancels out correlated errors

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Silicon Device Technology

• Qubits are phosphorus atoms in silicon
• Control with classical wires

Skinner02
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Fundamental Constraint
Quantum gates require classical control lines!
( Marcus 1997 )
( Nakamura, Nature 398, p. 786, 99 )
( Yablonovitch, 1999 )

• Quantum 20 nm
• Classical 100s of nm

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Quantum vs. Classical
Isailovic et al ACM TACO 2003
What if transistors were 3 orders of mag. smaller
than wires
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Architectural Implications
Communication is critical
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A simple quantum wire

• Short wire constructed from swap gates
• Each step requires 3 CNOT ops (swap)
• Key difference from classical
• qubits are stationary

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How far can you communicate?
Latency
lat T x D
Bandwidth
-?D
bw 1/T e
T time per swap D distance (bits) ? error
rate
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Recursive Structures
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Control Pulse Sequence

• 2-D layout (mentioned in Kane 00) moves
  electrons in parallel
• Simpler control
• Better electron separation
• Control signals still complicated!
• S-gate cascade
• A-gate sequence

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Swap control circuit
S-gate pulse cascade
Off-on A-gate pulse subsequence (2 off, 254 on)
A-gate pulse repeats 24 times
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Large!

• Control circuit area, 10um2
• Aggressive process, 30nm feature size
• Minimal design
• Swap cell area, 0.068um2

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SIMD Control

• Large control circuit/small swap cell ratio
  SIMD

Isailovic et al ACM TACO 2003
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Clustering

• Recursive scheme is overkill
• Dont error correct every operation
• 
  Oskin,Chong,Chuang IEEE Computer 02

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Space Savings
Shors
p10-6
Grovers
p10-6
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Time Savings
Shors
p10-6
Grovers
p10-6
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Building Block (I)

• Measurement unit computational Bell basis

Classical control
Measure
Qubit to measure
Classical 0,1 output with probability determined
by ?
Zero qubit
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Building Block (II)
EPR

• EPR generation unit

Classical control
Quantum output of an EPR state
EPR Generator
Zero qubits
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Building Block (III)
EX

• Entropy exchange unit

Polarized Light
P

Ground
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Building Block (IV)
Pur

• Purification unit error correction

Classical control
Purification Unit
Zero bits
Purified EPR states
EPR states to purify
Garbage state (to Entropy Exch)
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General-Purpose Architecture
Spin Polarized Electrons

• Teleportation connects comp. units
• Self-refreshing memory
• Parallel quantum ALU
• Classical microprocessor control
• Dynamic compilation
• Scheduling

Classical Microprocessor
Qubits
EX
Pur
EPR
Classical Bus
Quantum Bus