ADC Front-End Design Considerations for Telecommunication Satellite Applications

1

• ADC Front-End Design Considerations for
  Telecommunication Satellite Applications
• presented by
• Dr. Rajan Bedi
• rajan.bedi_at_astrium.eads.net
• UK EXPORT CONTROL TECHNOLOGY RATING
• 3A001.a.1.a, 3A001.a.2.a, 3C001.a, 3C001.b,
  3E001, 4E001.a, 4A003.a, 5E001.b.1
• Rated By P. Cornfield with reference to UK
  Export Control Lists (version INTR_B05.doc 30
  July
• 2006) which contains the following caveat The
  control texts reproduced in this guide are for
• information purposes only and have no force in
  law. Please note that where legal advice is
• required, exporters should make their own
  arrangements.
• Export licence Not required for EU countries.
  Community General Export authorisation EU001
• is valid for export to Australia, Canada,
  Japan, New Zealand, Norway, Switzerland USA.

2
Agenda

• Introduction
• Balun and ADC Modelling
• Simulation Results
• Conclusion Future Work

3
Differential ADCs

• Digital wideband telecommunication payloads use
  high-frequency differential ADCs.
• System noise accumulates in signals as they
  travel across a PCB or through long cables.
• Differential signals are highly immune to system
  noise due to the common-mode rejection of a
  differential ADC.
• System noise such as that induced from switching
  supplies, ground currents and EMI are reduced due
  to the common-mode rejection of a differential
  ADC.
• Differential signals cancel even-order harmonics
  providing better distortion performance than
  single-ended signals.
• A differential input doubles the ADCs useful
  dynamic range.

4
Single-Ended to Differential Conversion

• Prior to digitization, we need to convert the
  single-ended, down-converted baseband output to a
  differential signal.
• The conversion from single-ended to differential,
  transmission line effects and package parasitics,
  adversely affect the integrity of the analogue
  input to the ADC.
• These combined effects impact the maximum dynamic
  performance that can be achieved from the ADC.

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Single-Ended to Differential Conversion

• There are a number of conversion options
• Single-ended to differential amplifier
• RF Transformer
• There were no wideband space-grade differential
  amplifiers that had the required bandwidth and
  dynamic range.

6
Balun Transformer

• A balun transformer is to be used to convert the
  single-ended, down-converted baseband output to a
  differential signal.
• The balun also provides the necessary impedance
  matching between the single-ended input and the
  differential input resistance of the ADC.
• A centre-tapped secondary winding provides the
  freedom to set the common-mode level arbitrarily.
• The voltage gain provided by a step-up balun
  transformer introduces no non-linear,
  amplification noise.

7
Simplified Ideal Balun Specification
The balun converts the 50 ohm single-ended
baseband input into a differential signal driving
the100 ohm differential ADC input
resistance. Impedance Ratio Z Secondary
Impedance / Primary Impedance 2 Turns Ratio N
Secondary Turns / Primary Turns vZ v2 1.414
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Balun Imperfections

• Balun transformers are not perfect.
• Intrinsic parasitics affect the amplitude and
  phase balance of the differential output which
  could potentially result in increased even-order
  distortion in the ADC output spectrum.
• Baluns have a finite bandwidth and not always a
  flat amplitude response over the frequency range
  of interest.
• Baluns introduce an in-circuit insertion loss as
  well as a return loss.

9
Balun Imperfections

• Winding Resistance both the primary and
  secondary windings have resistance (copper loss)
  which reduces the expected load voltage.
• Magnetic Flux Leakage both the primary and
  secondary windings have leakage inductance caused
  by incomplete mutual coupling between the
  windings.
• Intra-Winding Capacitance there is always some
  stray capacitance between adjacent turns of each
  winding effective capacitance in parallel with
  each winding of the balun.

10
Balun Imperfections

• Inter-Winding Capacitance - there is stray
  capacitance between windings.
• Core Losses
• Eddy current loss which increases with frequency
• Hystersis loss which increases with flux density
• Magnetising inductance core loss
• Low-frequency behaviour of a balun transformer is
  influenced by the inductance of the primary
  winding.
• High-frequency behaviour of a balun transformer
  is influenced by the windings capacitances and
  series inductances.

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Model of a Lossy Non-Ideal Balun

• Primary and secondary leakage inductance IL
  and -RL at high freqs.
• Primary and secondary resistive winding loss
  IL at high freqs.
• Interwinding and Intrawinding capacitances IL
  at high freqs.
• Core losses IL and -RL at low freqs.

12
Simulation Environment

• A simulation environment has been developed to
  model the analogue front end which includes
• A VHDL-AMS behavioural model of a differential
  ADC which accounts for offset and gain error, DNL
  and INL.
• A SPICE model of a lossy balun transformer model
  which includes real balun parasitics.
• Transmission line interconnect effects between
  these components.

13
Simulation Environment

• The simulation environment is allowing us to
  investigate how the balun parasitics affect the
  output from the ADC.
• Sinusoidal and NPR analysis within this
  simulation environment.

14
ADC Simulation Results8-bit ADC model DNL
0.5 lsb, INL 1 lsb

• Single tone testing, Fin 47.5 MHz at 1 dBFS
• SFDR 52.5 dBc, SINAD 43.2 dB, SNR 43.9 dB
  ENOB 7 bits

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ADC Simulation Results8-bit ADC model DNL
0.5 lsb, INL 1 lsb
There is only 2.5 dB variation in SFDR as a
function of phase imbalance due to a slight
increase in H2.
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ADC Simulation Results8-bit ADC model DNL
0.5 lsb, INL 1 lsb

• SINAD decreases by 2.5 dB as a function of phase
  imbalance

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ADC Simulation Results8-bit ADC model DNL
0.5 lsb, INL 1 lsb

• SNR decreases by 2.5 dB as a function of phase
  imbalance

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ADC Simulation Results8-bit ADC model DNL
0.5 lsb, INL 1 lsb

• ENOB decreases by 0.41 bits as a function of
  phase imbalance

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ADC Simulation Results8-bit ADC model DNL
0.5 lsb, INL 1 lsb
There is 3.7 dB variation in SFDR as a function
of amplitude imbalance.
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ADC Simulation Results8-bit ADC model DNL
0.5 lsb, INL 1 lsb
Negligible variation in SINAD as a function of
amplitude imbalance.
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ADC Simulation Results8-bit ADC model DNL
0.5 lsb, INL 1 lsb
Minor variation in SNR as a function of amplitude
imbalance.
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ADC Simulation Results10-bit ADC model DNL
0.5 lsb, INL 1 lsb

• Single tone testing, Fin 45.625 MHz at 1
  dBFS
• SFDR 67.3 dBc, SINAD 54.9 dB, SNR 55.5 dB
  ENOB 8.92 bits

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ADC Simulation Results10-bit ADC model DNL
0.5 lsb, INL 1 lsb
There is only 1.7 dB variation in SFDR as a
function of phase imbalance, not due to H2.
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ADC Simulation Results10-bit ADC model DNL
0.5 lsb, INL 1 lsb

• SINAD decreases by only 0.8 dB as a function of
  phase imbalance

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ADC Simulation Results10-bit ADC model DNL
0.5 lsb, INL 1 lsb

• SNR decreases by only 1.2 dB as a function of
  phase imbalance

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ADC Simulation Results10-bit ADC model DNL
0.5 lsb, INL 1 lsb

• ENOB decreases by only 0.19 bits as a function
  of phase imbalance

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Conclusion

• A simulation environment has been developed that
  allows the analogue front-end of a digital
  payload to be modelled.
• Simulation results suggest that actual device
  amplitude and phase imbalances from standard
  product COTS baluns have limited impact on the
  dynamic performance of an ADC.
• Parameters such as 3dB bandwidth and flatness
  over the frequency range of interest maybe more
  important from a Systems/Payload perspective.

28
Future Work

• We are about to characterise a selection of COTS
  baluns using a VNA to measure the amplitude and
  phase imbalance ..
• These will then be used to convert a single-ended
  signal to a differential ADC input to correlate
  the measured data from actual hardware with
  simulation results.