Low power 32-bit bus with inversion encoding

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Low power 32-bit bus with inversion encoding

• Wei Jiang
• ELEC 6270

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Power Consumption by Bus

• High capacitance lines
• High switching activities
• Reduce power dissipation by reducing the number
  of transitions

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Bus Invert Encoding
Transmitter
Receiver
32
Conventional Bus
Transmitter
Receiver
ENCODER
DECODER
32
INV
Bus with Inversion Encoding
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Bus Invert Encoding

• To minimize transitions in bus with large
  capacitance
• Additional Line INV
• Encoding
• Di, if INV0
• Di XOR 1, if INV1
• Decoding
• Di XOR INV
• Proposed by M. R. Stan

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Design of Encoder
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Majority voter

• Majority voter circuit decides according to
  Hamming distance whether to invert or not the
  next value
• Digital voter accurate
• Analog voter simple
• Stan, TVLSI 1995

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Counter Comparator
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Falling Edge Detector/Indicator
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Design of Decoder
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Simulation Best Scenario
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Simulation Worst Scenario
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Signal Transitions
Total Power Dissipation
Power Dissipation of Transmitter
Power Dissipation of Receiver
Signals forms
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Simulation Average
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Conclusion

• Average power by transmitter/receiver (CL0)
• For conventional bus 0.8415mW
• For inverted bus 2.20745 mW
• Encoder/Decoder overhead 1.36595 mW
• Increase the power dissipation of low capacitance
  bus
• Reduce dynamical power dissipation by roughly 10
  if bus load capacitance per bit is 1pf 25 for
  2pf of load capacitance and more for even higher
  capacitance
• The actual power reduction depends on both the
  bus load capacitance and the number of
  transitions
• More than 17/close to 32 bus inversion may
  reducing power
• Less than 17 bus inversion may increase power

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Thank You

• Simulation
• TSMC 0.35um Process
• Synopsys HSPICE
• References
• M. R. Stan and W. P. Burleson, Bus-invert coding
  for low-power I/O, IEEE Trans. On VLSI Systems,
  Vol.3, No.1, pp.49-58, 1995
• T. Lindkvist et al, Deep Sub-Micron Bus Invert
  Coding, NORSIG 2004, p.133-136, June 2004