Xilinx Virtex-II Pro Evaluation Kit

1
A HW / SW Co-design Tool for Modern FPGAs with
FPGA-Embedded Processors
Institute for Software Integrated
Systems Vanderbilt University Jason Scott,
Sandeep Neema, Brandon Eames, Ted Bapty
Raytheon Sarir Khamsi, Troy Gangwer, Garrett
Wright, Andrew Vandivort
Design Space Exploration
System Synthesis
Model-based System Design
OPB CoreConnect Bus
PLB CoreConnect Bus
Components in FPGA Fabric
UART
Camera In
PLB /OPB Bridge
VPO
ACS PORT
VPI
VPO
VPI
Loc Out
DDR DRAM
PowerPC 405 Core
IFC
IFC
IFC
IFC
Dataflow Model Specifies Algorithm
Large Design-Space (1000s to 1020)
Apply System Constraints

• Efficient Interface Generation
• High bandwidth hw-sw communication

PowerPC
DSP
DSP
DSP
MATLAB on PC
FPGA Fabric
Virtex-II Pro
Manageable Set of Feasible Designs
Resource Model Specifies Target Platform
TI TMS320C6711 DSP Module
Correlation
Source
Sink
Multiply
IFFT
FFT
Spectral Correlation
Verification (Schedulability)
Simulation (Matlab)
Conv
Xilinx Virtex-II Pro Evaluation Kit with XC2VP7
Spatial Correlation
Stack of C67 DSP / FPGAs
Alternative Model Specifies Design
Flexibility Ex. Algorithm Alternative Spectral
vs Spatial