IMAPS Global Business Council Roadmap Process

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IMAPS Global Business CouncilRoadmap Process

• The Road Ahead

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The GBC Roadmap Team

• This Roadmap Process presentation was prepared by
  these members of the IMAPS Global Business
  Council National Technology Council
• Steve Adamson (sadamson_at_asymtek.com)
• Justin Blount (Justin.M.Blount_at_usa.dupont.com)
• Laurie Roth (lroth_at_kns.com)
• Lee Smith (lsmit_at_amkor.com)
• Andy Strandjord (andrew.strandjord_at_flipchip.com)
• Jie Xue (jixue_at_cisco.com)

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Topics

• Where does IMAPS fit in with the ITRS and iNEMI
  Roadmaps?
• What is the ITRS Roadmap and how does it work?
• What is the iNEMI Roadmap and how does it work?
• How does IMAPS interact with this Roadmap
  Process?
• Why IMAPS should be involved.
• IMAPS Areas of Focus.
• If you are already familiar with the ITRS iNEMI
  Roadmap Process, skip to slide 19
• The Roadmaps
• ITRS
• iNEMI
• Summary IMAPS Areas of Focus.

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ITRS iNEMI Packaging Roadmaps Intersect
IMAPS addresses the Semiconductor Packaging needs
of this space.
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What is the ITRS?

• The International Technology Roadmap for
  Semiconductors (ITRS) is an assessment of
  semiconductor technology requirements.
• The objective of the ITRS is to ensure
  advancements in the performance of integrated
  circuits.
• This assessment, called roadmapping, is a
  cooperative effort of global industry
  manufacturers and suppliers, government
  organizations, consortia, and universities.
• The ITRS identifies the technological challenges
  and needs facing the semiconductor industry over
  the next 15 years.
• It is sponsored by the European Semiconductor
  Industry Association (ESIA), the Japan
  Electronics and Information Technology Industries
  Association (JEITA), the Korean Semiconductor
  Industry Association (KSIA), the Semiconductor
  Industry Association (SIA), and Taiwan
  Semiconductor Industry Association (TSIA).
• SEMATECH is the global communication center for
  this activity. The ITRS team at SEMATECH also
  coordinates the USA region events.

http//public.itrs.net/
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ITRS Technology Working Groups

• The ITRS process encourages discussion and debate
  throughout the community about the requirements
  for success.
• The key factor in the success of the Roadmap is
  obtaining consensus on industry drivers,
  requirements, and technology timelines.
• The Technology Working Groups are the
  organizations that "build" the roadmaps.
• These representatives assess the state of
  technology and identify areas that may provide
  solutions.
• The TWG members also indicate opportunities for
  new research and innovation.
• These groups are made up of volunteer technology
  experts from chip manufactures, supplier
  companies, universities and academia, technology
  labs, and semiconductor technology consortia.
• The Technology Working Groups, also known as
  TWGs, are comprised of the technical disciplines
  of
• System Drivers
• Design
• Test and Test Equipment
• Process Integration, Devices, and Structures
• RF and Analog/Mixed-signal Technologies for
  Wireless Communications
• Emerging Research Devices and Materials
• Front End Processes
• Lithography
• Interconnect
• Factory Integration
• Assembly and Packaging This is the area where
  IMAPS will focus.
• Environment, Safety, and Health

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Example of ITRS Short Term Challenges
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iNEMI has strong industry support.
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iNEMI Roadmap Methodology

• iNEMI focusses on top level industry segments via
  their Product Emulator Groups.
• In addition, they address technology areas via
  their different Technology Working Groups.
• A cross-cut matrix ensures feedback between the
  various groups.

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iNEMI Technology Working Groups

• Business Processes/Technologies
• Product Lifecycle Information Management
• Design Technologies
• Environmentally Conscious Electronics
• Modeling, Simulation Design Tools
• Thermal Management
• Manufacturing Technologies
• Board Assembly
• Test, Inspection Measurement
• Final Assembly
• Component Subsystem Technologies
• Passive Components
• RF Components Subsystems
• Packaging This is one of the areas where IMAPS
  will focus.
• Semiconductor Technology
• Organic Substrates
• Mass Data Storage
• Connectors
• Energy Storage Systems

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iNEMI Cross-cut Matrix
A cross-cut matrix ensures feedback between the
various groups.
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Example of iNEMI short term challenges
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Update calendar for ITRS / iNEMI

• 2006 ITRS Roadmap release scheduled for December
  4, 2006.
• 2007 iNEMI Roadmap release scheduled for February
  2007 at APEX, Los Angeles.

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Why IMAPS should be involved.

• ITRS focuses mainly on front end wafer fab
  areas, with a chapter on Semiconductor Assembly
  Packaging.
• iNEMI focuses mainly on board level assembly,
  with a chapter on Semiconductor Assembly
  Packaging.
• ITRS/iNEMI are working together to align their
  Semiconductor Assembly Packaging Roadmaps.
• Many of the same people are on both teams.
• Some IMAPS members are also on both teams.
• IMAPS focus is on Semiconductor Assembly
  Packaging.
• Its a natural fit to take the output of the
  ITRS/iNEMI Semiconductor Assembly Packaging
  Roadmaps and use that output to direct IMAPS
  activities towards solving gaps in the roadmap.
• IMAPS corporate members will benefit by
  developing real industry solutions for real
  industry challenges.

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Global Semiconductor Packaging Materials Outlook
Market Size for Materials Market Opportunities
for IMAPS members.
Source SEMI Industry Research and Statistics and
TechSearch International, November 2005
This forecast was supplied courtesy of SEMI
Techsearch International. The full report is
available from SEMIs web catalog at www.semi.org
.
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Launched The Road Ahead in Advancing
Microelectronics 4/06
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Roll-out plan for IMAPS to address roadmaps

• Form a GBC Roadmap Team.- DONE
• GBC Roadmap Team creates a roadmap template (red
  brick) and identifies current gaps on the
  existing roadmaps. - DONE
• GBC Roadmap Team communicates those gaps to the
  NTC.
• GBC and NTC structure future IMAPS events to
  focus on those gaps ongoing.
• Dave Saums to give short presentation at LED
  Thermal ATWs in September 2006.
• Meantime, GBC/NTC to support ITRS/iNEMI updates
  with input communicate back to IMAPS
  issues/trends.
• Use IMAPS members on the ITRS/iNEMI roadmap TWGs
  to facilitate communication Laurie Roth, Howard
  Imhof....and other volunteers.

"Red Brick" template "Red Brick" template "Red Brick" template "Red Brick" template "Red Brick" template  
2006 2007 2008 etc    
  X        
           
           
           
  Manufacturing solutions exist and are being optimized. Manufacturing solutions exist and are being optimized. Manufacturing solutions exist and are being optimized. Manufacturing solutions exist and are being optimized. Manufacturing solutions exist and are being optimized.
  Manufacturing solutions are know. Manufacturing solutions are know. Manufacturing solutions are know. Manufacturing solutions are know.  
X Interim solutions are known. Interim solutions are known. Interim solutions are known.    
  Manufacturable solutions are NOT known. Manufacturable solutions are NOT known. Manufacturable solutions are NOT known. Manufacturable solutions are NOT known.  
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Recommended Areas of Focus for IMAPS Members

• Develop Feasible Embedded Components.
• Develop Enhanced Materials to Enable Wafer Level
  Packaging.
• Bring Solutions to Resolve Thermal Management
  Issues.
• Develop New Materials to Reduce System Cost While
  Delivering the Necessary Performance.
• Close the Gap Between Chip and Substrate
  Interconnect Density.
• Resolve the issues low K and Cu bring to
  Packaging.

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The Roadmaps
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The complete chapter can be downloaded from the
ITRS website http//www.itrs.net/Common/2005ITRS/
AP2005.pdf The following slides contain key
excerpts.
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ITRS 2005 Semiconductor Packaging Roadmap Table
of Contents
All of these topics and those on the next slide
are comprehensively covered in the ITRS
Roadmap. This presentation will focus on the key
challenges only.

• Packaging Materials Requirements
• New Materials
• Embedded and Integrated Passives
• Assembly and Packaging Infrastructure Challenges
• Electrical Design Requirements
• Cross Talk
• Power Distribution and Power Subsystem
• Thermo-mechanical Challenges in Electronic
  Packaging
• Mechanical Challenges
• Mechanical Modeling and Simulation and Validation
• Thermal Modeling and Simulation and Validation
• Equipment Requirements for Emerging Package Types
• Potential Solutions
• Wafer Level Packaging
• Chip to Next Level Interconnect
• Package to Board Interconnect
• Fine Pitch Ball Grid Array/CSP Packages
• Socketed Parts
• Embedded and Integrated Passives

• Chapter Scope
• Difficult Challenges
• Technology Requirements
• Single Chip Packages
• High Pin-Count Packages
• Wafer Level Packaging
• System in a Package (Multi-chip Packages, 3D
  Packaging)
• Flexible Substrates and Interconnect
• Optoelectronic Packaging
• RF Packaging
• MEMS
• Medical and Bio Chip Packaging
• Biocompatibility
• Bio Packaging Reliability
• Integrated Circuit
• Manufacturing
• Cost
• Reliability
• Package and Interconnect Characterization and
  Simulation

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ITRS 2005 Semiconductor Packaging Roadmap Table
of Contentscontinued

• System in Package (SiP) System Level
  Integration
• Types/Categories of SiPs
• Side by Side Placement (Horizontal Packages)
• Stacked Structures
• Package-on-Package (POP), Package-in-Package
  (PiP)
• Stacked Die Packages
• Chip to Chip/Wafer Structure
• Embedded Structures
• Technologies for SiP
• Wafer level SiP and 3 D Integration Technologies
• Technologies for Embedded Devices
• Challenges for SiP
• Thermal management
• System in Package Outlook
• Wafer Thinning
• Glossary of Terms
• Cross-Cut ITWG Issues
• Design
• Factory Integration

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ITRS Single Chip Package

• Incremental improvements in traditional assembly
  technologies will not be sufficient to meet
  market requirements.
• The substrate dominates the cost of single chip
  packaging.
• Cost per pin has been trending up, instead of
  down.
• Operating temperatures are a problem in harsh
  environments.
• Higher frequency chip-to-board speeds for
  peripheral buses.

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ITRS High Pin-Count Packages

• Package pin count grows as higher frequency and
  higher power density demand more power and ground
  pins.
• Substrate technology requires micro-vias, blind
  buried vias, stacked vias and tighter lines and
  spacing.
• Substrate technology advances lead to significant
  cost increases for design/test and a reduced
  supplier base.
• System-in-Package will become more important to
  reduce the need for high density interconnects in
  the package substrate and the PCB.

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ITRS Chip-to-Package Substrate
Development work is required for finer pitch
in-line wire bond area array flip chip.
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ITRS Package Substrate Physical Properties
Near Term
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ITRS Package Substrate Physical Properties
Long Term
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ITRS System-in-Package - definitions

• SiP enables reduction in size, weight, cost
  power.
• System-on-Chip can address size, weight power,
  but at cost, design test premiums.
• SiP integrates multiple functions/devices in a
  single package.
• Can integrate different elements such as MEMS,
  opto, bio....
• Includes 3D stacked die packaging.
• Requires Known Good Die.

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ITRS System-in-Package Requirements
The number of stacked die and the number of die
in a SiP are challenges.
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ITRS Thinned Wafers
Long term challenge for extreme thin packages.
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ITRS Wafer Level Packaging

• Near term challenges
• I/O pitch between 150 µm - 250 µm gt100 I/O
• Solder joint reliability
• Wafer thinning and handling technologies
• Compact ESD structures
• TCE mismatch compensation for large die

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ITRS Flexible Substrates

• Near term challenges
• Conformal low cost organic substrates
• Small and thin die assembly
• Handling in low cost operation

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ITRS Interconnect
It is very challenging to maintain packaging
reliability with strong chip-to-package
interaction resulting from new materials, new
processes, and new interconnect features at the
Si level.
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ITRS Interconnect (contd)
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ITRS Optoelectronic Packaging

• Package Sealing
• Hermetic sealing to protect the optical devices -
  TO header butterfly packaging.
• Non-hermetically sealed organic packaging for
  cost sensitive applications.
• Alignment
• lt 0.5 µm alignment between single mode fiber
  optical device for high data rate applications.
• 5 to 10 µm alignment accuracy for cost sensitive
  applications, using relatively large diameter
  polymer optical fiber (POF)
• Adhesive to assure alignment through succeeding
  high temperature processes product usage life.
• Materials
• POF material improvement in attenuation reduction
  and data rate increase is required.
• Material development for poly-clad-silica (PCS)
  fiber.
• Optically clear molding compound or clear glob
  tops for optical windows.
• Vertical integration to include more
  functionality in a package.
• Wafer-level-packaging (WLP) process to integrate
  lenses or other micro-opticalelectro-mechanical
  system (MOEMS) devices, and to provide
  environmental protection for a VCSEL wafer.
• Some micro-optical components, e.g. polymer
  waveguides and beam reflectors, may be embedded
  in the SiP substrate.
• A BGA based SiP may house optical connectors,
  laser diodes, photodetectors, CMOS IC containing
  receivers/drivers and multiplexer/demultiplexer,
  plus RF connectors, and decoupling capacitors.

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ITRS RF Packaging

• Many of the technology challenges for RF
  packaging arise from the fact that the IC
  packaging engineering practice, technology
  knowledge base, and manufacturing infrastructures
  have been based upon digital IC packaging
  developed in the last forty odd years.
• Issues
• The inductance characteristics associated with
  bonding wires and leaded packages, and effect of
  molding compound materials limit the RF
  performance.
• RF package modeling tools and materials
  properties database for package design and
  device-package co-design for the broad spectrum
  of RF market applications.
• Improvements in materials propertiesmolding
  compounds, underfills, substrates are required.
• Being able to embed passive components in LTCC.
• To meet the low cost challenges, embedded
  inductance and capacitance components and
  networks in organic packaging for RF applications
  must be diligently pursued.
• Tools to enable device package co-design in SIP
  packages will be very important.

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ITRS MEMS
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ITRS Medical Bio Chip Packaging

• BIOCOMPATIBILITY
• No interaction with body tissues and fluids.
• No inflammatory reactions.
• No toxicity to bio-organisms.
• No outgassing or other decay products that may be
  harmful to bio-organisms.
• Must be chemically inert to various
  concentrations of bio-reagents including ethanol.
  
• May include high flow rates with significant back
  pressure.
• BIO PACKAGING RELIABILITY
• Major concerns are patient safety and risk
  mitigation.
• For life-sustaining devices, component failure
  rate as low as 100 ppm, few ppm critical failure
  rate.
• Challenge to capture low occurrence failures in
  reliability testing.
• EMI is a major concern.
• Pressure requirements in a barometric pressure
  chamber or while scuba diving.
• Defibrillation devices could generate significant
  localized heating in the high voltage charging
  circuit when delivering therapy, challenging the
  package substrate and PCB.
• MANUFACTURING
• In accordance with regulatory requirements for
  medical devices
• Requirements for control of the manufacturing
  environment, labeling of the packages, and
  documentation.

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ITRS Cost

• Today packaging costs often exceed die
  fabrication costs.
• Leadfree solders.
• Low K High K dielectrics.
• Higher processing temperatures.
• Wider range of environmental temperatures.
• More efficient thermal management needed.

40
ITRS Reliability Simulation
New failure modes caused by new materials needed
to meet environmental and performance
requirements, result in significant challenges in
field reliability prediction based on accelerated
lab testing for broad product application field
requirements.

• The introduction of the new materials and
  structures to meet environmental, heat and speed
  requirements are posing new reliability
  challenges.
• New technology will be required to meet the
  reliability goals including
• New reliability tests such as drop tests for
  mobile products.
• Correlation between field- and laboratory
  testing.
• Improved methods for failure detection and
  analysis (e.g., X-ray, acoustic, nano-deformation
  and localized residual stress measurement.)
• Materials and interface characterization.
  Interfacial delamination will continue to be a
  critical reliability hazard that is worsened by
  the trends to larger chips, new materials and
  increased layer count. More layers require the
  understanding of more interfaces.
• Simulation and modeling for life time prediction
  (e.g., multi-field coupling, structure-property
  correlation, ab-initio methods, modular and
  parametric approaches).

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ITRS Packaging Materials
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ITRS Infrastructure

• Electrical design
• Cross talk
• Power distribution power subsystem
• Thermo-mechanical
• Modeling Simulation
• Equipment

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www.inemi.org

• The iNEMI Roadmap is only available for download
  to TWG members or on-line purchase.
• The following slides contain key excerpts from
  the 2007 Roadmap Update-in-progess.

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Recommended Areas of Focus for IMAPS
MembersSummary

• Develop Feasible Embedded Components.
• Develop Enhanced Materials to Enable Wafer Level
  Packaging.
• Bring Solutions to Resolve Thermal Management
  Issues.
• Develop New Materials to Reduce System Cost While
  Delivering the Necessary Performance.
• Close the Gap Between Chip and Substrate
  Interconnect Density.
• Resolve the issues low K and Cu bring to
  Packaging.

49
Back Up
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ITRS Difficult Challenges 32 nm Near Term
The ITRS Roadmap segments issues into those that
are Near Term affect Wafer Nodes 32 nm and
those that are Long Term affect Wafer Nodes lt32
nm.
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ITRS Difficult Challenges 32 nm Near Term
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ITRS Difficult Challenges 32 nm Near Term
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ITRS Difficult Challenges 32 nm Near Term
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ITRS Difficult Challenges lt 32 nm Long Term