A Deficit Round Robin Input Arbiter for NetFPGA

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ADeficit Round Robin Input Arbiterfor NetFPGA

• Jonathan Woodruff

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Fair Queuing
Described by John Nagle

• Packetwise Round Robin Isnt Fair
• Bitwise Round Robin Is Fair
• Approximate
• Downsides
• Adds Complexity
• Adds New Queuing Stage

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Deficit Round Robin
By George Varghese

• Counters on the Queues
• Approximates Fair Queuing
• Downside
• May Add New Queuing Stage

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NetFPGA Deficit Round Robin

• New Queuing Stage
• Two Flows
• Input Port
• Type of Service
• Input Port Option is Ineffective in Congestion

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Simple Deficit Round Robin

• Use the Input Arbiter Queuing Stage
• Fair Queuing with No Added Complexity
• Useful When Ports Flows
• i.e. at the edge of the network where each port
  represents a single system.

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DRR Input Queues
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Input Arbiter
Size Count
Selector
Data
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Header Parser
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TAIL
IP
Module
MAC
ARP
Route
N-Hop IP
IP
?
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Output Multiplexer
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Input Arbiter
Queue 1
Queue 2
Queue 3
Queue 4
Queue 5
Queue 6
Queue 7
Size Count
Data
Selector 0
Selector 1
Data 0
Data 1
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Bandwidth Sharing
Mb/s
Deficit Quanta
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Ping vs. Deficit Quanta
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Throughput vs. Deficit Quanta
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Questions?