EECS 150 - Components and Design Techniques for Digital Systems Lec 06

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EECS 150 - Components and Design Techniques for
Digital Systems Lec 06 Minimizing Boolean
Logic9/16-04

• David Culler
• Electrical Engineering and Computer Sciences
• University of California, Berkeley
• http//www.eecs.berkeley.edu/culler
• http//www-inst.eecs.berkeley.edu/cs150

2
Review

• Combinational logic
• Truth Tables vs Boolean Expressions vs Gates
• Minimal Operators
• And / Or / Not, NAND, NOR
• New Friends
• XOR, EQ, Full Adder
• Boolean Algebra
• , , , assoc, comm, distr., .
• Manipulating Expressions and Circuits
• Proofs Term rewriting Exhaustive Enumeration
• Simplifications
• De Morgans Law
• Duality
• Canonical and minimal forms
• Sum of products
• Product of sums

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Review Relationship Among Representations

• Theorem Any Boolean function that can be
  expressed as a truth table can be written as an
  expression in Boolean Algebra using AND, OR, NOT.

How do we convert from one to the
other? Optimizations?
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Review Canonical Forms

• Standard form for a Boolean expression - unique
  algebraic expression directly from a true table
  (TT) description.
• Two Types
• Sum of Products (SOP)
• Product of Sums (POS)

• Sum of Products (disjunctive normal form, minterm
  expansion). Example
• minterms a b c f f
• abc 0 0 0 0 1
• abc 0 0 1 0 1
• abc 0 1 0 0 1
• abc 0 1 1 1 0
• abc 1 0 0 1 0
• abc 1 0 1 1 0
• abc 1 1 0 1 0
• abc 1 1 1 1 0

One product (and) term for each 1 in f f abc
abc abc abc abc f abc abc
abc
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Review Sum of Products (cont.)

• Canonical Forms are usually not minimal
• Our Example
• f abc abc abc abc abc (xy xy
  x)
• abc ab ab
• abc a (xy x y x)
• a bc
• f abc abc abc
• ab abc
• a ( b bc )
• a ( b c )
• ab ac

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Review Canonical Forms

• Product of Sums (conjunctive normal form, maxterm
  expansion). Example
• maxterms a b c f f
• abc 0 0 0 0 1
• abc 0 0 1 0 1
• abc 0 1 0 0 1
• abc 0 1 1 1 0
• abc 1 0 0 1 0
• abc 1 0 1 1 0
• abc 1 1 0 1 0
• abc 1 1 1 1 0
• Mapping from SOP to POS (or POS to SOP) Derive
  truth table then proceed.

One sum (or) term for each 0 in f f
(abc)(abc)(abc) f
(abc)(abc)(abc) (abc)(abc)
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Incompletely specified functions

• Example binary coded decimal increment by 1
• BCD digits encode decimal digits 0 9 in bit
  patterns 0000 1001

A B C D W X Y Z0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 0 0
0 1 0 0 0 1 1 0 0 1 1 0 1 0 0 0 1 0 0 0 1 0 1 0 1
0 1 0 1 1 0 0 1 1 0 0 1 1 1 0 1 1 1 1 0 0 0 1 0 0
0 1 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 X X X X 1 0 1 1
X X X X 1 1 0 0 X X X X 1 1 0 1 X X X X 1 1 1 0 X
X X X 1 1 1 1 X X X X
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Outline

• Review
• De Morgans to transform SofP into simple 2-level
  forms
• Uniting Law to reduce SofP
• N-cube perspective
• Announcements
• Karnaugh Maps
• Examples
• Reduction Algorithm

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Putting DeMorgans to work

• DeMorgans Law
• (a b) a b (a b) a b
• a b (a b) (a b) (a b)
• push bubbles or introduce in pairs or remove
  pairs.

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Transformation to Simple Gates
Involution x (x)
Sum of Products
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Implementations of Two-level Logic

• Sum-of-products
• AND gates to form product terms(minterms)
• OR gate to form sum
• Product-of-sums
• OR gates to form sum terms(maxterms)
• AND gates to form product

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Two-level Logic using NAND Gates

• Replace minterm AND gates with NAND gates
• Place compensating inversion at inputs of OR gate

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Two-level Logic using NAND Gates (contd)

• OR gate with inverted inputs is a NAND gate
• de Morgan's A' B' (A B)'
• Two-level NAND-NAND network
• Inverted inputs are not counted
• In a typical circuit, inversion is done once and
  signal distributed

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Two-level Logic using NOR Gates

• Replace maxterm OR gates with NOR gates
• Place compensating inversion at inputs of AND gate

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Two-level Logic using NOR Gates (contd)

• AND gate with inverted inputs is a NOR gate
• de Morgan's A' B' (A B)'
• Two-level NOR-NOR network
• Inverted inputs are not counted
• In a typical circuit, inversion is done once and
  signal distributed

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The Uniting Theorem

• Key tool to simplification A (B' B) A
• Essence of simplification of two-level logic
• Find two element subsets of the ON-set where only
  one variable changes its value this single
  varying variable can be eliminated and a single
  product term used to represent both elements

F A'B'AB' (A'A)B' B'
A B F 0 0 1 0 1 0 1 0 1 1 1 0
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Boolean cubes

• Visual technique for identifying when the uniting
  theorem can be applied
• n input variables n-dimensional "cube
• Neighbors address differs by one bit flip

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Mapping truth tables onto Boolean cubes

• Uniting theorem combines two "faces" of a cube
  into a larger "face"
• Example

F
A B F 0 0 1 0 1 0 1 0 1 1 1 0
ON-set solid nodesOFF-set empty nodesDC-set
?'d nodes
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Three variable example

• Binary full-adder carry-out logic

A B Cin Cout 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 1 1 0 0
0 1 0 1 1 1 1 0 1 1 1 1 1
the on-set is completely covered by the
combination (OR) of the subcubes of lower
dimensionality - note that 111is covered three
times
Cout BCinABACin
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Higher dimensional cubes

• Sub-cubes of higher dimension than 2

F(A,B,C) ?m(4,5,6,7) on-set forms a
squarei.e., a cube of dimension 2 represents an
expression in one variable i.e., 3
dimensions 2 dimensions
A is asserted (true) and unchanged B and C vary
This subcube represents the literal A
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m-dimensional cubes in a n-dimensional Boolean
space

• In a 3-cube (three variables)
• 0-cube, i.e., a single node, yields a term in 3
  literals
• 1-cube, i.e., a line of two nodes, yields a term
  in 2 literals
• 2-cube, i.e., a plane of four nodes, yields a
  term in 1 literal
• 3-cube, i.e., a cube of eight nodes, yields a
  constant term "1"
• In general,
• m-subcube within an n-cube (m lt n) yields a term
  with n m literals

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Announcements

• Homework 2 due Friday
• Reading 2.5-2.8 (rest of ch 2)
• Homework 3 posted

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Karnaugh maps

• Flat map of Boolean cube
• Wraparound at edges
• Hard to draw and visualize for more than 4
  dimensions
• Virtually impossible for more than 6 dimensions
• Alternative to truth-tables to help visualize
  adjacencies
• Guide to applying the uniting theorem
• On-set elements with only one variable changing
  value are adjacent unlike the situation in a
  linear truth-table

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Karnaugh maps (contd)

• Numbering scheme based on Graycode
• e.g., 00, 01, 11, 10
• 2n values of n bits where each differs from next
  by one bit flip
• Hamiltonian circuit through n-cube
• Only a single bit changes in code for adjacent
  map cells

13 1101 ABCD
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Adjacencies in Karnaugh maps

• Wrap from first to last column
• Wrap top row to bottom row

111
011
110
010
001
B
101
C
100
000
A
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Karnaugh map examples

• F
• Cout
• f(A,B,C) ?m(0,4,6,7)

obtain thecomplementof the function by
covering 0swith subcubes
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More Karnaugh map examples
G(A,B,C)
F(A,B,C) ?m(0,4,5,7)
F' simply replace 1's with 0's and vice versa
F'(A,B,C) ? m(1,2,3,6)
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K-map 4-variable interactive quiz

• F(A,B,C,D) ?m(0,2,3,5,6,7,8,10,11,14,15)F

A
D
B
find the smallest number of the largest possible
subcubes to cover the ON-set (fewer terms with
fewer inputs per term)
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Karnaugh map 4-variable example

• F(A,B,C,D) ?m(0,2,3,5,6,7,8,10,11,14,15)F

A
D
B
find the smallest number of the largest possible
subcubes to cover the ON-set (fewer terms with
fewer inputs per term)
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Karnaugh maps dont cares

• f(A,B,C,D) ??m(1,3,5,7,9) d(6,12,13)
• without don't cares
• f

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Karnaugh maps dont cares (contd)

• f(A,B,C,D) ??m(1,3,5,7,9) d(6,12,13)
• f A'D B'C'D without don't cares
• f with don't cares

don't cares can be treated as1s or 0sdepending
on which is more advantageous
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Design example two-bit comparator
we'll need a 4-variable Karnaugh map for each of
the 3 output functions
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Design example two-bit comparator (contd)
K-map for EQ
K-map for LT
K-map for GT
LT EQ GT
(A xnor C) (B xnor D)
Canonical PofS vs minimal?
LT and GT are similar (flip A/C and B/D)
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Design example two-bit comparator (contd)
two alternative implementations of EQ with and
without XOR
XNOR is implemented with at least 3 simple gates
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Design example 2x2-bit multiplier
A2 A1 B2 B1 P8 P4 P2 P1 0 0 0 0 0 0 0 0 0 1 0 0
0 0 1 0 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 0 0 0
0 1 0 0 0 1 1 0 0 0 1 0 1 1 0 0 1 1 1 0 0 0 0
0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 0 1
1 0 0 0 0 0 0 0 1 0 0 1 1 1 0 0 1 1 0 1 1 1
0 0 1
block diagram and truth table
4-variable K-map for each of the 4 output
functions
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Design example 2x2-bit multiplier (contd)
K-map for P4
K-map for P8
P4 A2B2B1' A2A1'B2
P8 A2A1B2B1
K-map for P2
K-map for P1
P1 A1B1
P2 A2'A1B2 A1B2B1' A2B2'B1 A2A1'B1
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Design example BCD increment by 1
I8 I4 I2 I1 O8 O4 O2 O10 0 0 0 0 0 0 1 0 0 0 1 0
0 1 0 0 0 1 0 0 0 1 1 0 0 1 1 0 1 0 0 0 1 0 0 0 1
0 1 0 1 0 1 0 1 1 0 0 1 1 0 0 1 1 1 0 1 1 1 1 0 0
0 1 0 0 0 1 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 X X X X
1 0 1 1 X X X X 1 1 0 0 X X X X 1 1 0 1 X X X X 1
1 1 0 X X X X 1 1 1 1 X X X X
block diagram and truth table
4-variable K-map for each of the 4 output
functions
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Design example BCD increment by 1 (contd)
O8
O4
O2
O1
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Definition of terms for two-level simplification

• Implicant
• Single element of ON-set or DC-set or any group
  of these elements that can be combined to form a
  subcube
• Prime implicant
• Implicant that can't be combined with another to
  form a larger subcube
• Essential prime implicant
• Prime implicant is essential if it alone covers
  an element of ON-set
• Will participate in ALL possible covers of the
  ON-set
• DC-set used to form prime implicants but not to
  make implicant essential
• Objective
• Grow implicant into prime implicants (minimize
  literals per term)
• Cover the ON-set with as few prime implicants as
  possible(minimize number of product terms)

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Examples to illustrate terms
minimum cover AC BC' A'B'D
minimum cover 4 essential implicants
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Algorithm for two-level simplification

• Algorithm minimum sum-of-products expression
  from a Karnaugh map
• Step 1 choose an element of the ON-set
• Step 2 find "maximal" groupings of 1s and Xs
  adjacent to that element
• consider top/bottom row, left/right column, and
  corner adjacencies
• this forms prime implicants (number of elements
  always a power of 2)
• Repeat Steps 1 and 2 to find all prime
  implicants
• Step 3 revisit the 1s in the K-map
• if covered by single prime implicant, it is
  essential, and participates in final cover
• 1s covered by essential prime implicant do not
  need to be revisited
• Step 4 if there remain 1s not covered by
  essential prime implicants
• select the smallest number of prime implicants
  that cover the remaining 1s

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Algorithm for two-level simplification (example)
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Summary

• Boolean Algebra provides framework for logic
  simplification
• De Morgans transforms between gate types
• Uniting to reduce minterms
• Karnaugh maps provide visual notion of
  simplifications
• Algorithm for producing reduced form.
• Question are there programmable logic families
  that are simpler than FPGAs for the canonical
  forms?