Interconnect-Power Dissipation in a Microprocessor

1
Interconnect-Power Dissipation in a Microprocessor

• N. Magen, A. Kolodny, U. Weiser, N. Shamir

Intel corporation Technion - Israel Institute of
Technology
2
Interconnect-Power Definition

• Interconnect-Power is dynamic power consumption
  due to interconnect capacitance switching
• How much power is consumed by Interconnections ?
• Future generations trends ?
• How to reduce the interconnect power ?

0.13 µm cross-section, source - Intel
3
Background

• Power is becoming a major design issue
• Scope Dynamic power, the majority of power
• P SAFiCi V2 f
• This work focuses on the capacitance term

4
Outline

• Research methodology
• Interconnect Power Analysis
• Power-Aware Router Experiment
• Interconnect Power Prediction
• Summary

5
Case study

• Low-power, state-of-the-art µ-processor
• Dynamic switching power analysis
• Interconnect attributes
• Length
• Capacitance
• Fan Out (FO)
• Hierarchy data
• Net type
• Activity factors (AF)
• Miscellaneous.

6
Interconnect Length Model

• Total wire length
• Stitched across hierarchies
• Summed over repeaters
• Net model

7
Activity Factors Generation
Power test vectors generation (worst case for
high power, unit stressing)
RTL full-chip simulation (results in blocks
primary inputs Activity,Probability)
Monte-Carlo based block inputs generation (based
on the RTL statistics)
Transistor level simulation - per block (Unit
delay, tuning for glitches)
Per node activity factor
Source -Intel Pentium M Processor Power
Estimation, Budgeting, Optimization, and
Validation, ITJ 2003
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Outline

• Research methodology
• Interconnect Power Analysis
• Power-Aware Router Experiment
• Interconnect Power Prediction
• Summary

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Interconnect Length Distribution
Source Shekhar Y. Borkar, CRL - Intel
10
Interconnect Length Distribution
Nets vs. Net Length

• Log Log scale
• Exponential decrease with length
• Global clock not included

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Total Dynamic Power
Total Power vs. Net Length

• Total Dynamic Power
• Global clock not included
• Local nets 66
• Global nets 34

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Total Dynamic Power Breakdown
Global clock included
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Power Breakdown by Net Types
Global clock included
Interconnect power (Interconnect only)
Total power (Gate, Diffusion and Interconnect)
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Interconnect Power Breakdown

• Interconnect consumes 50 of dynamic power
• Clock power 40 (of Interconnect and total)
• 90 of power consumed by 10 of nets
• Interconnect design is NOT power-aware !
• Predictive model can project the interconnect
  power.

Total power
Interconnect power
Local signals
Local clock
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Outline

• Research methodology
• Interconnect Power Analysis
• Power-Aware Router Experiment
• Interconnect Power Prediction
• Summary

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Experiment - Power-Aware Router

• Routing Experiment optimizing processors blocks
• Local nodes (clock and signals) consume 66 of
  dynamic power
• 10 of nets consume 90 of power
• Min. spanning trees can save over 20
  Interconnect power
• Routing with spacing can save up to 40
  Interconnect power

Small blocks local clock network
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Power-Aware Router Flow
Clock tree high FO, long lines, very active
Avoiding congestion
Rip-up not high power nets
Followed by downsizing
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Results - Power Saving
Downsize saving
Average
Router saving
Average saving results 14.3 for ASIC blocks 1
1 - Estimated based on clock interconnect power
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Outline

• Research methodology
• Interconnect Power Analysis
• Power-Aware Router Experiment
• Interconnect Power Prediction
• Summary

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Future of Interconnect Power
Dynamic Power breakdown
Gate
Diffusion
Interconnect
Source - ITRS 2001 Edition adapted data
Technology generation µm
Interconnect power grows to 65-80 within 5
years !

• (using optimistic interconnect scaling)

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Interconnect Power Prediction
Number of Nets (normalized)
Interconnect length projection
100

• The number of nets vs. unit length Modified
  Davis model
• The dynamic power average breakdown

10
1
0.1
Upper local bound
0.01
Lower global bound
Power
0
0.001
Dynamic power breakdown
Interconnect
Power
Diffusion
Gate
Local
Intermediate
Global
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Interconnect Power Model

• Multiplication of the number of interconnects
  with power breakdowns gives

Projected dynamic power vs. net length
Power (normalized)
Length µm
The power model matches processor power
distribution !
23
Outline

• Research methodology
• Interconnect Power Analysis
• Power-Aware Router Experiment
• Interconnect Power Prediction
• Summary

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Summary

• Interconnect is 50 of the dynamic power of
  processors, and getting worse.
• Interconnect power-aware design is recommended
• Clock consumes 40 of interconnect power.
• Clock interconnect spacing is suggested
• Interconnect power is sum of nearly all net
  lengths and types.
• Router level Interconnect power reduction
  addresses all
• Interconnect power has strong dependency on the
  hierarchy
• Per Hierarchy analysis and optimization algorithms

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Future Research

• Interconnect Power characterization and
  prediction
• Investigate Interconnect power reduction
  techniques
• Interconnect-Spacing for power
• Interconnect Power-Aware physical design
• Aspect Ratio optimization for power
• Architectural communication reduction

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Questions ?
27
BACKUP-Slides
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Processor Case Study

• Analysis subject Processor, 0.13 µm
• 77 million transistors, die size of 88 mm2
• Data sources (AF, Capacitance, Length)
• Excluded L2 cache, global clock, analog units

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Global Communication
Global Power vs. Test Power

• Global power is important
• Global power is mostly IC
• For higher power benchmarks Global power is
  higher
• G-clock excluded

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Benchmark Selection

• High power test benchmarks
• Worst case design
• Suitable for thermal design, power grid design
• Average power is a fraction of peak power
• Unit stressing benchmarks
• Averaging of all high power benchmarks
• High node coverage

ITC logo
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Interconnect Power Implications

• Interconnect power can be reduced by minimizing
  switched capacitance
• Fabrication process (wire parameters)
• Power-driven physical design
• Logic optimization for power
• Architectural interconnect optimization

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Interconnect Capacitance
Global Capacitance breakdown

• Side-cap is increasing 70 to 80

self-cap.
Side-cap.
Technology generation µm
Source - ITRS 2001 Edition adapted data
The majority of interconnect capacitance is
side-capacitance !
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Fabrication Process Aspect Ratio (AR)

• Interconnect AR
• Low AR Low Interconnect power
• Low AR High resistance
• Frequency Modeling
• Local average gate, average IC
• Global optimally buffered global IC

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Aspect Ratio Trade offs
Freq. And Power vs. Relative AR

• Power depends on cap.
• Frequency
• Local gates and IC cap.
• Global mostly IC RC
• Per layer AR optimization !
• Scaling ? more power save, less frequency loss

Local path speed
Power
Global path speed
Relative AR
Aspect Ratio optimization can save over 10 of
dynamic power !
35
Physical Design - Spacing
0.13 µm global IC cap. vs. spacing

• Spacing can save up to 40
• About 30 is with double space
• Spacing advantages scaling, frequency,
  reliability, noise,easy to modify

Capacitance
2X
3X
4X
min. space
Spacing
Wire spacing can save up to 20 of the dynamic
power !
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Spacing calculation

• Back of an envelope estimation
• 10 of Interconnect ? 90 power
• X2 spacing extra 20 wiring
• Global clock not spaced (inductance)
• Global clock is 20 of interconnect power
• Save 30 of (90-20) 20
• Interconnect is 50 ? 10 power saveExpected 20
  with downsizing
• Minor losses - congestion

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µ-Architecture - CMP
Gen. 1
Gen. 2

• Comparing two scaling methods, by IC power.

• IC - predicted by Rent
• L2 - identical, minor
• Clock - Identical !

• Same average AF.
• Result 5 less dynamic power for CMP

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Power criticalvs.Timing critical
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Outline

• Research methodology
• Interconnect Power Analysis
• Future Trends Analysis
• Interconnect Power Implications
• Summary

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Interconnect Length Prediction

• Technology projections - ITRS
• Interconnect length predictions
• ITRS model 1/3 of the routing space- most
  optimistic
• Davis model
• Rents rule based
• Predicts number of nets as function ofthe
  number of gates and complexity factors
• Models calibrated based on the case study

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Rents parameters
Rents rule T k N r T of I/O
terminals (pins) N of gates K avg.
I/Os per gate r Rents exponent can be 0 lt
r lt 1 , but common - (simple) 0.5 lt r lt 0.75
(complex)
T terminals
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Donaths length estimation model
For the i-th level
There are
For each block there are
Assuming two terminal nets
The nets of the i-1 level must be substracted.
Nets for level i ni
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Average interconnection length
The wires can be of two types A and D.
LA
LD
The average ri
Overall
equals
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Davis Model

• From Rents rule
• IDF
• Where ,
• Interconnect total number and lengthNets
  Length
• Multipoint Length

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Davis Model - extension

• Constant factor favors shorter nets.
• Short P2P net has higher chance to be a part of
  a multipoint net.
• Correction factor
• Length

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RMST - Example
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Total Dynamic Power
Total Power vs. Net Length

• Total Dynamic Power
• Global clock not included
• Local nets 66Global nets 34

Power (normalized)
0
Length µm
48
Local and Global IC
Local Power breakdown vs. Net Length

• Local and Global IC are different
• Number by Length breakdown
• IC breakdown cap and power
• Fan out
• Metal usage
• AF is similar

Global Power breakdown vs. Net Length
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Benchmarks Comparison
Global Dynamic power vs. Length
High power tests show similar behavior to average
SPEC !
50
Interconnect Peaks
Total wire length vs. Length
4
3
2
1
0
10
Length µm
Length µm
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ITRS Power Trends

• The ITRS power projection interconnect power
  reduction that happens in 2006-2007 is based on
• Aggressive voltage reduction
• Low-k dielectric improvements
• The devices capacitance increase by 30 (trend
  -15)
• The combined effect
• Interconnect power reduction (relative to
  voltage)
• Device power remains constant

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Dynamic power - ITRS trend
Dynamic power projection
Power (normalized)
Technology generation µm
The Black curve is the ITRS maximum heat removal
capabilities
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Power-Aware Flow

• The reduced IC cap allows for driver downsizing
• On average it reduced the dynamic power by 1.4 of
  the IC power saving
• Downsizing is timing verified
• Cells downsizing reduced the total area and
  leakage by 0.4
• No signal spacing was appliedover 30 unused
  metal
• Post-layout optimization are possible

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FUBS description

• A medium, randomly picked
• B small, highest clock power
• C small, good potential
• D medium, good potential
• E worse than average

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Miller Factor - Power

• Opposite direction switching-
• The current
• Energy
• That is 4 times a single switching
  energy.Decoupling by Miller factor of 2.
• Same direction switching gt no current.Decoupling
  by Miller factor of 0.
• Average case Miller factor of 1 suitable for
  power- average case sum metric.

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Routing Model

• Via blockage
• Router efficiency 0.6
• Power grid 20 of routing
• Clock grid 10 of top tier
• More accurate than ITRS 2001.