Design Oriented Model for Symmetric DG MOSFET

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Design Oriented Model for Symmetric DG MOSFET
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Outline

• Scaling limits in BULK MOSFET
• The Double-Gate (DG) MOSFET
• Compact model for symmetric DG MOSFET
• Model validation vs. 2D simulations
• Model implementation in VHDL-AMS
• Conclusion

3
Outline

• Scaling limits in BULK MOSFET
• The Double-Gate (DG) MOSFET
• Compact model for symmetric DG MOSFET
• Model validation vs. 2D simulations
• Model implementation in VHDL-AMS
• Conclusion

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Scaling limits of BULK MOSFET

• Limit for supply voltage (lt0.6V)
• Limit for further scaling of tox (lt2nm)
• Minimum channel length Lg50nm
• Discrete dopant fluctuations
• Dramatic short-channels effects (SCE)

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Outline

• Scaling limits in BULK MOSFET
• The Double-Gate (DG) MOSFET
• Compact model for symmetric DG MOSFET
• Model validation vs. 2D simulations
• Model implementation in VHDL-AMS
• Conclusion

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How can we follow Moores law ?

• ? By moving to DG MOSFETs
• DG might be the unique viable alternative to
  build nano MOSFETs when Lglt50nm
• Because
• - Better control of the channel from the gates
• - Reduced short-channel effects
• - Better Ion/Ioff
• - Improved sub-threshold slope (60mV/decade)
• - No discrete dopant fluctuations

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DG MOSFET structure
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Typical values for DG MOSFET

• tox1nm tsi10nm Lg25nm

Is the behavior still classical  ? Can we
still use 3D DOS, drift-diffusion approach,
surface potential concept ? Yes and No
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Electrostatic considerations

• Depending on tsi , 2D discrete levels cannot be
  ignored in principle.
• For very thin films (lt5nm), 2D states are so
  confined that electrostatic correction can be
  ignored (FD-Baccarani).
• For relatively thick films, 2D levels can be
  ignored, reverting to the more classical
  description (3DBoltz.-Taur).
• For intermediate thicknesses, 2D states should
  be coupled to electrostatic (Ge Fossum).

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Outline

• Scaling limits in BULK MOSFET
• The Double-Gate (DG) MOSFET
• Compact model for symmetric DG MOSFET
• Model validation vs. 2D simulations
• Model implementation in VHDL-AMS
• Conclusion

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Model Taurs approach 1

• 3D but with volume inversion
• No more charge sheet approximation concept
• Analytical solution of charges and current
• However,
• not a truly analytical model (iteration needed)
• NO ANALYTICAL solution for Vds ? 0 hence no
  solution for transcapacitances

1 Y. Taur, X. Liang, W. Wang and H. Lu, IEEE
Electron Device Letters, vol. 25, no. 2, pp.
107-109, 2004.
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• In the original approach, the mobile charges are
  evaluated through complex functions
• No insight into electrical quantities
• For instance, the drain current is given by

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Our new approach

• An EKV-like formulation 2 !
• Normalization of charges and current as in EKV
  but we have 2 gates

2 J.-M. Sallese, F. Krummenacher, F.
Prégaldiny, C. Lallement, A. Roy and C. Enz, A
design oriented charge-based current model for
symmetric DG MOSFET and its correlation with the
EKV formalism, Solid-State Electronics, vol. 49,
pp. 485-489, 2005.
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Our new approach

• Mobile charge density vs. potentials
• And we still use the drift-diffusion concept
• For tsi 1nm, we get the EKV relations(very
  interesting for the transcapacitances)

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Our new approach

• Formulation of DG reverts to the classicalcharge
  sheet approximation for bulk and SOI MOSFETs
• This implies that the transcapacitances can be
  obtained in the same way as in bulk MOSFETs 3
• In addition, the new model accurately describes
  important central characteristics such as gm /Id

3 F. Prégaldiny, F. Krummenacher, D. Birahim,
F. Pêcheux, J.-M. Sallese and C. Lallement, A
fully analytical compact model for symmetric DG
MOSFETs, submitted to ESSDERC.
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Outline

• Scaling limits in BULK MOSFET
• The Double-Gate (DG) MOSFET
• Compact model for symmetric DG MOSFET
• Model validation vs. 2D simulations
• Model implementation in VHDL-AMS
• Conclusion

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The 2D simulations

• Structures developed under Atlas (Silvaco)

tox2nm tsi5?50nm LgWg1µm
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Model vs. exact Taurs formulation
? Normalized inversion charge density
as a function of Vgs Symbols Taurs
model lines our analytical model
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Model vs. 2D simulations
? Drain current Ids as a function of
Vgs at different Vds Symbols 2D
results lines our analytical model
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Model vs. 2D simulations
? Drain current Ids as a function of
Vgs at different tsi
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Model vs. 2D simulations
? Transcapacitances as a function of
Vgs at different Vds Symbols 2D
results lines our analytical model
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The gm /Id concept in DG MOSFET
J.-M. Sallese, F. Krummenacher, F. Prégaldiny, C.
Lallement, A. Roy and C. Enz, A design oriented
charge-based current model for symmetric DG
MOSFET and its correlation with the EKV
formalism, Solid-State Electronics, vol. 49, pp.
485-489, 2005.
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Outline

• Scaling limits in BULK MOSFET
• The Double-Gate (DG) MOSFET
• Compact model for symmetric DG MOSFET
• Model validation vs. 2D simulations
• Model implementation in VHDL-AMS
• Conclusion

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VHDL-AMS code the structure
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VHDL-AMS code the entity
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VHDL-AMS code the function qqi
To determine the normalized charge for both
source and drain sides
Computed with no iteration !
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VHDL-AMS code the architecture
ARCHITECTURE equ OF mos_dg IS . .
. quantity vg1n, vg2n, vsn, vdn
real quantity Inf, Inr, Xf,
Xr real quantity Csg, Cdg, Cds, Csd,
Cgd, Cgs, Css, Cdd, Cgg real . . .
quantity Vd across D to electrical_ground
quantity Vg1 across S to electrical_ground
quantity Vg1 across G1 to
electrical_ground quantity Vg2 across G2
to electrical_ground quantity
Ids through D to S . . . -- Function
definition pure function qqi(Vg1n,Vreal)
return real is . . . BEGIN -- Normalized
voltages vg1n Vg1/UT vg2n
Vg2/UT vsn Vsn/UT vdn
Vg1/UT -- Drain current of the SOI DG
MOSFET ids IDO(-4.0qqi(vg1n,
vdn)2.0 4.0 qqi(vg1n, vsn)2.0 ) --
Capacitances Inf Inr Xr
Xf Csg Cdg /
END
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Simulation resultsperformed with the AMS
software 4.0.2.1 from Mentor Graphics
IDS(VGS) at VDS 0.25, 0.5, 0.75, 1V
IDS
VGS
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Simulation results
IDS(VDS) at VGS 0.5, 0.75, 1V
IDS
VDS
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Outline

• Scaling limits in BULK MOSFET
• The Double-Gate (DG) MOSFET
• Compact model for symmetric DG MOSFET
• Model validation vs. 2D simulations
• Model implementation in VHDL-AMS
• Conclusion

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Conclusion

• Undoped DG MOSFETs are promising candidatesfor
  ultra deep-submicron VLSI technology
• The 2D simulations of different DG MOSFET
  structures have been carried out
• A truly analytical compact model has been
  developed
• All quantities in the model are expressed in
  terms of normalized variables ? helpful for
  developing efficient design methodologies
• This long-channel core model would need to be
  augmented with second-order effects (mobility
  reduction, SCE, quantum effects)