Achievements

1
Achievements Perspectives of MIMOSA Sensors
(MAPS) for Vertexing ApplicationsChristine
Hu-Guo (IPHC)on behalf of IPHC (Strasbourg)
IRFU (Saclay) collaboration

• Outline
• Achieved MAPS (Monolithic Active Pixel Sensors)
  performances
• RD for improving MAPS performances
• Increase readout speed ? Fast readout
  architecture
• Applications and perspectives
• Improve radiation tolerance
• Projection beyond present (2D sensors)
  perspectives
• Conclusion

2
Development of MAPS for Charged Particle Tracking

• In 1999, the IPHC CMOS sensor group proposed the
  first CMOS pixel sensor (MAPS) for future vertex
  detectors (ILC)
• Numerous other applications of MAPS have emerged
  since then
• 10-15 HEP groups in the USA Europe are
  presently active in MAPS RD
• Original aspect integrate sensitive volume (EPI
  layer) and front-end readout electronics on the
  same substrate
• Charge created in EPI, excess carries propagate
  thermally, collected by NWELL/PEPI , with help
  of reflection on boundaries with P-well and
  substrate (high doping)
• Q 80 e-h / µm ? signal lt 1000 e-
• Compact, flexible
• EPI layer 1015 µm thick
• thinning to 3040 µm permitted
• Standard CMOS fabrication technology
• Cheap, fast multi-project run turn-around
• Room temperature operation
• Attractive balance between granularity, material
  budget, radiation tolerance, read out speed and
  power dissipation
• BUT
• Very thin sensitive volume ? impacts signal
  magnitude (mV!)
• Sensitive volume almost un-depleted ? impacts
  radiation tolerance speed
• Commercial fabrication (parameters) ? impacts
  sensing performances radiation tolerance

R.T.
3
Achieved Performances with Analogue Readout

• MAPS provide excellent tracking performances
• Detection efficiency 100
• ENC 10-15 e-
• S/N gt 20-30 (MPV) at room temperature
• Single point resolution µm, a function of pixel
  pitch
• 1 µm (10 µm pitch), 3 µm (40 µm pitch)

4
Radiation tolerance (preliminary)

• Ionising radiation tolerance
• O(1 M Rad) (MIMOSA15, test cond. 5 GeV e-, T
  -20C, tint180 µs)
• tint ltlt 1 ms, crucial at room temperature
• Non ionising radiation tolerance depends on
  pixel pitch
• 20 µm pitch 2x1012 neq /cm2 , (Mimosa15, tested
  on DESY e- beams, T - 20C, tint 700 µs)
• 5.81012neq/cm² values derived with standard and
  with soft cuts
• 10 µm pitch 1013 neq /cm2 , (MIMOSA18, tested at
  CERN-SPS , T - 20C, tint 3 ms)
• parasitic 12 kGy gas ? N ?
• Further studies needed
• Tolerance vs diode size, Readout speed, Digital
  output, ... , Annealing ??

Integ. Dose Noise S/N (MPV) Detection Efficiency
0 9.0 1.1 27.8 0.5 100
1 Mrad 10.7 0.9 19.5 0.2 99.96 0.04
Fluence (1012neq/cm²) 0 0.47 2.1 5.8 (5/2) 5.8 (4/2)
S/N (MPV) 27.8 0.5 21.8 0.5 14.7 0.3 8.7 2. 7.5 2.
Det. Efficiency () 100. 99.9 0.1 99.3 0.2 77. 2. 84. 2.
Fluence (1012neq/cm²) 0 6 10
Q cluster (e-) 1026 680 560
S/N (MPV) 28.5 0.2 20.4 0.2 14.7 0.2
Det. Efficiency () 99.93 0.03 99.85 0.05 99.5 0.1
5
System integration

• Industrial thinning (via STAR collaboration at
  LBNL)
• 50 µm, expected to 30-40 µm
• Ex. MIMOSA18 (5.55.5 mm² thinned to 50 µm)
• Development of ladder equipped with MIMOSA chips
  (coll. with LBNL)
• STAR ladder (lt 0.3 X0 ) ? ILC (lt0.2 X0 )
• Edgeless dicing / stitching ? alleviate material
  budget of flex cable

6
MAPS performance Improvement
RD organisation 4 (5) simultaneous prototyping
lines

• ?Architecture of pixel array organised in //
  columns read out
• Pre-amp and CDS in each pixel
• A/D 1 discriminator / column (offset
  compensation)
• Power vs Speed
• Power ? Readout in a rolling shutter mode
• Speed ? Pixels belonging to the same row are read
  out simultaneously
• MIMOSA8 (2004), MIMOSA16 (2006), MIMOSA22
  (2007/08)

• ?Zero suppression circuit
• Reduce the raw data flow of MAPS
• Data compression factor ranging from 10 to 1000,
  depending on the hit density per frame
• SUZE-01 (2007)

• ?45 bits ADCs (103 ADC per sensor)
• Potentially replacing column-leveldiscriminators
• 5 bits ?sp 1.71.6 µm 4 bits ?sp lt 2 µm for
  20 µm pitch
• Next step integrate column-level ADC with pixel
  array

• ?Serial link transmission with clock recovery
• Prototype (2008-2009)

?Voltage regulator DC-DC converter
7
MIMOSA22 SUZE-01 Test Results

• MIMOSA22 (15 µm EPI) 136 x 576 pixels 128
  column-level discriminators
• SUZE-01
• Lab. test

• Laboratory test
• Temporal Noise 0.64 mV ? 12 e-
• FPN 0.22 mV ? 4 e-

• Beam test at CERN SPS (120 GeV pions)
• Threshold 4 mV ? 6 x s noise
• Detection Efficiency gt 99.5
• Single point resolution lt 4 µm
• Fake rate lt 10-4

8
MIMOSA26 1st MAPS with Integrated Ø
CMOS 0.35 µm OPTO technology, Chip size 13.7 x
21.5 mm2

• Pixel array 576 x 1152, pitch 18.4 µm
• Active area 10.6 x 21.2 mm2
• In each pixel
• Amplification
• CDS (Correlated Double Sampling)

• Integration time 100 µs
• ? R.O. speed 10 k frames/s
• Hit density 106 particles/cm²/s

• Testability several test points implemented all
  along readout path
• Pixels out (analogue)
• Discriminators
• Zero suppression
• Signal transmission

• Row sequencer
• Width 350 µm

• 1152 column-level discriminators
• offset compensated high gain preamplifier
  followedby latch

• Zero suppression logic

• Reference Voltages Buffering for 1152
  discriminators

• I/O PadsPower supply PadsCircuit control
  PadsLVDS Tx Rx

• Memory management
• Memory IP blocks

• Readout controller
• JTAG controller

• Current Ref.
• Bias DACs

• PLL, 8b/10b optional

9
Test MIMOSA26 (Lab. beam test)

• Measured temporal noise 0.6-0.7 mV and FPN
  0.3-0.4 mV for pixel array with its associated
  discriminators.
• These values are equivalent to those obtained
  with Mimosa22.
• It shows a good uniformity of the whole 576 x
  1152 pixels with the 1152 discriminators
• 30 MIMOSA26 chips are tested (only 1 "dead")
• The characterization of Mimosa26 is complemented
  by the beam tests (Sept. 2009)
• 6 MIMOSA26 chips running simultaneously at
  nominal speed
• Tracking successful
• data analysis is underway, preliminary results
  show similar performances as MIMOSA22

10
MIMOSA26 Final Sensor for EUDET Beam Telescope

• EUDET supported by the European Union in the 6th
  Framework Programme
• Provide to the scientific community an
  infrastructure aiming to support the detector RD
  for the ILC
• JRA1 (Joint Research Activity) High resolution
  pixel beam telescope (BT)
• Two arms each equipped with three layers of pixel
  sensors (MIMOSA)
• DUT is located between these arms and moveable
  via X-Y table
• EUDET beam telescope specifications
• High extrapolated resolution lt 2 µm
• Large sensor area 2 cm2
• High read-out speed 10 k frame/s
• Hit density up to 106 hits/s/cm2

Pixel Sensor
MIMOSA26
13.7 mm
(DUT)
21.5 mm
Being Mounted on EUDET beam telescope

• Preliminary test results from the EUDET
  collaboration
• 3 MIMOSA26 chips mounted as DUT in BT
  demonstrator in July
• BT tracks reconstructed in the 3 planes ?
  residues compatible with ssp 3.5-4 µm

11
Extension of MIMOSA-26 to STAR

• Final HFT (Heavy Flavour Tracker) - PIXEL sensor
  
• MIMOSA-26 with active surface 1.7
• 1088 col. of 1024 pixels ? 1.1 million pixels
• Pitch 18.4 µm ? (20.0 x 18.8 mm²)
• Integration time 200 µs
• Design from now ? fab. Feb. 2010
• 1st physics data expected in 2011/12

• Critical points
• Reduction of power consumption
• Radiation tolerance improvement
• Also
• Integrated voltage reference
• High speed transmission

Pixel Vx Detector
22.4 mm
Inner Layer 10 ladders
Outer Layer 30 ladders 10 sensors / ladder
20.4 mm
STAR Detector Upgrade
12
Extension of MIMOSA-26 to CBM/FAIR ILC

• Micro Vertex Detector (MVD) of the CBM H.I. fixed
  target expt
• 2 double-sided stations equipped with MIMOSA
  sensors
• MIMOSA-26 with double-sided read-out ? readout
  speed !
• Active surface 2 x 1152 columns of 256 pixels
• 21.2 x 9.4 mm2
• tint. 40 µs
• lt 25 µs in lt 0.18 µm techno.
• Prototyping until 2012 ? start of physics in
  2013/14 (?)
• Vertex detector of the ILC
• tint. 25 µs (innermost layer) ? double-sided
  readout
• tint. 100 µs (outer layer) ? Single-sided
  readout
• 2 µm (4-bit ADC, 20 µm) lt ?sp lt 3 µm (discri. 14
  µm pitch)
• Pdiss lt 0.11 W/cm² 1/50 duty cycle

ILD design 2 options

• Critical points
• Power pulsing
• Design for the innermost layer
• Small pixel pitch
• Faster readout speed

3 double layers
5 single layers
13
Radiation Tolerance Improvement

• Ionising radiation tolerance 1. Special layout
• Diode level (already realized) Remove thick
  oxide surrounding N-well diode by replacing with
  thin-oxide? without design rule violation!!
• Pixel circuit level ELT for the transistors
  connected to the detection diode
• 2. Minimise integration time ? Increase readout
  speed
• Minimise leakage current

14
Radiation Tolerance Improvement

• Non ionising radiation toleranceHigh resistivity
  sensitive volume ? faster charge collection
• Exploration of a VDSM technology with depleted
  (partially 30 µm) substrate
• Project "LePix" driven by CERN for SLHC trackers
  (attractive for CBM, ILC and CLIC Vx Det.)
• Exploration of a technology with high resistivity
  thin epitaxial layer
• XFAB 0.6 µm techno 15 µm EPI (? O(103)?.cm),
  Vdd 5 V (MIMOSA25)
• ? Benefit from the need of industry for
  improvement of the photo-sensing elements
  embedded into CMOS chip

TCAD Simulation 15 µm high resistivity EPI
compared to 15 µm standard EPI
For comparison standard CMOS technology, low
resistivity P-epi
high resistivity P-epi size of depletion zone
size is comparable to the P-epi thickness!
15
MIMOSA25 in a high resistivity epitaxial layer
MIMOSA25
saturation -gt gt90 of charge is collected is 3
pixels -gt very low charge spread for depleted
substrate
16x96 Pitch 20µm
To compare standard non-depleted EPI
substrate MIMOSA15 Pitch20µm, before and after
5.8x1012 neq/cm2

• 20 µm pitch, 20C, self-bias diode _at_ 4.5 V, 160
  µs read-out time
• Fluence (0.3 / 1.3 / 3)1013 neq/cm2
• Tolerance improved by gt 1 order of mag.
• Need to confirm ?det (uniformity !) with beam
  tests

16
Using 3DIT to improve MAPS performances

• 3DIT are expected to be particularly beneficial
  for MAPS
• Combine different fabrication processes
• Resorb most limitations specific to 2D MAPS
• Split signal collection and processing
  functionalities, use best suited technology for
  each Tier
• Tier-1 charge collection system ? Epitaxy
  (depleted or not), deep N-well ? ? ultra thin
  layer? X0 ?
• Tier-2 analogue signal processing? analogue, low
  Ileak, process (number of metal layers)
• Tier-3 mixed and digital signal processing
• Tier-4 data formatting (electro-optical
  conversion ?)
• Run in Chartered - Tezzaron technology
• 130 nm, 2-Tier run with "high"-res substrate
  (allows m.i.p. detection)
• Tier A to tier B bond? Cu-Cu bond
• 3 D consortium coordinated by FermiLab
• FermiLab
• INFN
• IN2P3-IRFU
• Univ. of Bonn
• CMP

17
IPHC IRFU 3D MAPS

• Delayed R.O. Architecture for the ILC Vertex
  Detector
• Try 3D architecture based on small pixel pitch,
  motivated by
• Single point resolution lt 3 µm with binary output
• Probability of gt 1 hit per train ltlt 10
• 12 µm pitch
• ?sp 2.5 µm
• Probability of gt 1 hit/train lt 5
• Split signal collection and processing
  functionalities
• Tier-1 A sensing diode amplifier, B shaper
  discriminator
• Tier-2 time stamp (5 bits) overflow bit
  delayed readout
• ? Architecture prepares for 3-Tier perspectives
  12 µm
• Tier-1 CMOS process adapted to charge collection
• Tier-2 CMOS process adapted to analogue mixed
  signal processing
• Tier-3 digital process (ltlt 100 nm ????)

18
IPHC 3D MAPS Self Triggering Pixel Strip-like
Tracker (STriPSeT)

• Combine Tezzaron/Chartered 2-tiers process with
  XFAB high resistivity EPI process
• Tier-1 XFAB, 15 µm depleted epitaxy ? ultra thin
  sensor!!!
• Fully depleted ? Fast charge collection (5ns) ?
  should be radiation tolerant
• For small pitch, charge contained in less than
  two pixels
• Sufficient (rather good) S/N ratio defined by the
  first stage
• charge amplification ( gtx10) by capacitive
  coupling to the second stage
• Tier-2 Shaperless front-end (Pavia Bergamo)
• Single stage, high gain, folded cascode based
  charge amplifier, with a current source in the
  feedback loop ? Shaping time of 200 ns very
  convenient good time resolution
• Low offset, continuous discriminator
• Tier-3 Digital Data driven (self-triggering),
  sparsified binary readout, X and Y projection of
  hit pixels pattern
• Matrix 256x256 ? 2 µs readout time

• DBI Direct Bond Interconnect, low temperature
  CMOS compatible direct oxide bonding with
  scalable interconnect for highest density 3D
  interconnections (lt 1 µm Pitch, gt 108/cm /cm²
  Possible)

19
IRFU IPHC 3D MAPS RSBPix

• FAST R.O. architecture aiming to minimise power
  consumption
• Subdivide sensitive area in small matrices
  running INDIVIDUALLY in rolling shutter mode
• Adapt the number of raws to required frame r.o.
  time
• ? few µs r.o. time may be reached (???)
• Planned also to connect this 2 tier circuit to
  XFAB detector tier

20
Conclusion

• 2D MAPS have reached necessary prototyping
  maturity for real scale applications
• Beam telescopes allowing for ?sp few µm 106
  particles/cm²/s
• Vertex detectors requiring high resolution very
  low material budget
• The emergence of fabrication processes with
  depleted epitaxy / substrate opens the door to
• Substantial improvements in read-out speed and
  non-ionising radiation tolerance
• "Large pitch" applications ? trackers (e.g. Super
  LHC )
• Translation to 3D integration technology
• Resorb most limitations specific to 2D MAPS
• T type density, peripheral insensitive zone,
  combination of different CMOS processes
• Offer an improved read-out speed O(µs) !
• Many difficulties to overcome (ex. heat, power)
• RD in progress ? 2009/10 important step for
  validation of this promising technology