RISC vs. CISC

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RISC vs. CISC

• Dhiraj Parashar
• Shiva Prasad Behera
• Vivek Sharma

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Overview

• Introduction
• Key arguments
• Comparisons
• Post-RISC
• Current Trends

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CISC Evolution

• Storage and Memory
• High cost of memory.
• Need for compact code.
• Support for high-level languages
• Ease of adding new microinstructions
• Marketing Strategy

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CISC Effects

• Moved complexity from s/w to h/w
• Compact code
• Ease of compiler design (HLLCA)
• Easier to debug
• Lengthened design times
• Increased design errors

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RISC Evolution

• Increasingly cheap memory
• Improvement in compiler technology
• Patterson Make the common case fast

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RISC Effect

• Move complexity from h/w to s/w
• Provided a single-chip solution
• Better use of chip area
• Better Speed
• Feasibility of pipelining
• Single cycle execution stages
• Uniform Instruction Format

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Key arguments

• RISC argument
• for a given technology, RISC implementation will
  be faster
• current VLSI technology enables single-chip RISC
• when technology enables single-chip CISC, RISC
  will be pipelined
• when technology enables pipelined CISC, RISC will
  have caches
• CISC argument
• CISC flaws not fundamental (fixed with more
  transistors)
• Moores Law will narrow the RISC/CISC gap (true)
• software costs will dominate (very true)

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Role of CompilerRISC vs. CISC

• CISC instruction
• MUL ltaddr1gt, ltaddr2gt
• RISC instructions
• LOAD A, ltaddr1gt
• LOAD B, ltaddr2gt
• MUL A, B
• STORE ltaddr1gt
• RISC is dependent on optimizing compilers

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Comparisons

• The Case for RISC (1980)
• Introductory paper advocating RISC
• Colwell et al. (1985)
• Comparison studies misleading
• Envisions use of techniques from both
• Clark, Bhandarkar (1990)
• MIPS M/2000 vs. VAX 8700
• Unfair comparison (?!)

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Post-RISC Architecture

• Additional functional units for superscalar
• Additional non-RISC (but fast) instructions
• Increased pipeline depth
• Branch prediction
• Out of order execution

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Current Trends

• P6 - x86 instructions decoded into RISC-like
  instructions (ROps)
• Intel called this hack CRISC. This concept was
  so moronic that even Intel could not market it!
• IA-64 - dependence on compilers for scheduling
• Athlon both direct execution and
  micro-programmed instructions

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Thanks!