Design of the Front-end Electronics for the GOSSIPO chip.

1
Design of the Front-end Electronics for the
GOSSIPO chip.

• Vladimir Gromov
• Electronics Technology
• NIKHEF, Amsterdam,
• the Netherlands
• CERN, July the 22th, 2005

2

• 
  Highlights.
• Main functionalities of the GOSSIPO.
• Main objectives and principal block diagram of
  the prototype of the chip .
• Evaluation of the parasitic capacitances at the
  input of the charge-sensitive preamplifier.
• Injection of the input test signal.
• Design and performance of the charge-sensitive
  preamplifier.
• Design and performance of the current comparator
  and output LVDS driver.
• Design and performance of the bias circuit.
• Conclusion and plans.

3
The GOSSIPO chip.(Gas On Slimmed Silicon Pixel)
Cathode (drift) plane
Cluster1
Cluster2
1mm, 400Volts
Cluster3
Micromegas
50um, 400Volts
Silicon wafer with read-out electronics on it
Input pixel
20um
The Input signal.
Shape of the current signal coming on the pixel
pad
Time-walk vs pulse height distribution
Input current, nA
ion component, Qi 90
Gain8000
Gain4000
electron component, Qe10
Gain2000
0 10 20 30
time,ns
Time-walk curve
Signal, electrons
THR350e
4

• Main features of the GOSSIPO chip.
• There will no silicon sensor on the chip due to a
  novel concept of the particle detection that
  allows to circumvent major constrains related to
  that.
• Low input parasitic capacitance and no need for
  the detector leakage current compensation at the
  input are the reasons to expect an outstanding
  performance of the design.
• Objectives
  for the prototype.
• Testing of the performance and the
  functionality of the Front-end electronics on the
  bare chip (without InGrid and
  with InGrid on it).
• The design is
  expected to demonstrate
• a) low-threshold operation
  (THR350e).
• b) fast pulse response (d-response
  peaking time 36ns , real signal response
  peaking time 52ns ).
• c) low analog power dissipation (
  1.7uW/channel for 1.2V supply).
• d) low channel-to-channel threshold
  dispersion (sTHR 140e).
• e) low parasitic feedback
  cross-talk.

5

• Principal block diagram of the GOSSIPO front-end
  circuit.

Charge sensitive preamplifier
Bias generator
Current Comparator with DC hysteresis
LVDS driver
Voltage-to-current converter
Bias control
Cfb 1fF
Vref
Ron 2GO
Rfb 80MO
Cc 200fF
Idet(t)
Cpar 30fF
Rl 1kO
Rl 1kO
Ithr42nA
Channel1
Channel2
Outputs
Channel3
Channel4
Charge sensitive preamplifier
Voltage follower
Cfb 1fF
Rfb 80MO
Idet(t)
Cpar 30fF
Channel5
6
Parasitic capacitances associated with the input
pad.

noise
peaking time

charge collection

Micromegas
Cp-grid
Cp-grid
Cp-grid
Cp-p
Cp-p
Input pad
Substrate of the wafer
Cp-sub
Cp-sub
Cpar Cp-grid Cp-p Cp-sub ,
where Cp-sub is pad-to-substrate
capacitance coupling

Cp-grid is
pad-to-Micromegas capacitance coupling

Cp-p
is pad-to-pad capacitance coupling .
7
Evaluation of the pad-to-Micromegas parasitic
capacitances Cp-grid.


Model for analytical calculations of the
pad-to-Micromegas parasitic capacitance.
R - is a radius of the pad. The pad is a circle.
d - is pad-to-Micromegas distance.
Ideal uniformly charged disk
- is vacuum dielectric constant.
e
0
R
D
Ideal boundless plane
C1.8fF when R25um, d50um
8
Evaluation of the pad-to-substrate parasitic
capacitances Cp-sub in 0.13um CMOS technology.


Layout of the input pad coupling in 0.13um CMOS
technology (CMOS8SF, flavour LM 6_2).

• Capacitive parasitics based on the physical
  design of the layout
• have been extracted within DIVA Extract rules
  supplied in the
• Design Kit. Both available methodologies
  (CDS_coeffgen_Cap
• and Raphael_Cap) have been used.
• Suggested Diva Deck Extraction
  Methodology
• (from the PDK Users guide)
  
• generate a trial test structure which mimic
  possible design
• geometries as much as possible.
• run extraction tool for both methodologies.
• review the capacitance numbers and use the tool
  that gives the
• more pessimistic results. Compare the numbers to
  hand
• calculations or a 3D field solver.

R
Input pad (LM, copper 0.55um)
MQ, copper 0.55um
Via 2x2, 0.8um x 0.8um
M6, copper 0.32um
M5, copper 0.32um
M4, copper 0.32um
6um
M3, copper 0.32um
M2, copper 0.32um
M1, copper 0.29um
PC
30
25 20 Cp-sub 15 fF 10 5 0
Cp-sub27fF R25um,
Substrate
Extraction done by DIVA with CDS_coeffgen_Cap
option
Analytical calculation
Extraction done by DIVA with Raphael_Cap option
0 5 10 15
20 25
R , um
9
Evaluation of the pad-to-pad parasitic
capacitances Cp-p in 0.13um CMOS technology.


Model for analytical calculations of the
pad-to-pad parasitic capacitance.
2.5 2 Cp-p 1.5 fF 1 0.5 0

Extraction done by DIVA with Raphael_Cap option
Extraction done by DIVA with CDS_coeffgen_Cap
option
Analytical calculation on the basis of the model.
where b is dimension of the pad,
c is thickness of the pad,
a is pad-to-pad distance,
e0 is vacuum dielectric constant,
er is relative permittivity of the
medium
0 5 10 15
20 a ,um
Evaluation of the input pad-to-pad capacitances
in 0.13um CMOS technology (CMOS8SF, flavour LM
6_2). Large pads (b30um)
a
b
b
Input pad
Input pad
Cp-p
c0.55um
Pad-to-pad layout
10
Injection of the input test signal.


Cpar Cpar Cin , therefore Cinltlt Cpar
30fF
Cfb 1fF
Charge sensitive preamplifier
Rfb 80MO
Uin 20mV
QinCin Uin 0.06fC (350e)
Cpar 30fF
Upulse(t)
Rt50O
Cin 3fF
Vertical Parallel Plate (VPP) capacitor in LM
layer.

40um
Passive pad
Test input
a1800nm
Active pad
Passive pad
d550um
Cfringe3.2fF
!!! Accuracy of the fringe capacitors.
?a50nm, ?a/a3 (lithography
accuracy) 25

?d140nm, ?d/d 25 (LM layer thickness
accuracy)
11
The charge-sensitive preamplifier. The feedback
capacitance.
1. Charge sensitivity Uamplitude Qdet /
Cfb 2. Charge collection (input impedance)
Cin A Cfb 140fF
Cin gtgt Cpar 30fF
Cfb 1fF
Rfb 80MO
Qdet
U(t)
Idet(t)
Cpar 30fF
C 0.5fF
A140
Coaxial-like layout of the input interconnection.
Extraction with the parasitics.

40um
40um
Input pad
0.18um
0.2um
Cp-sub 23fF
Cfb 1fF
!!! Accuracy of the fringe capacitor is
25 (metal layers accuracy)
C 0.5fF
Substrate
12
The charge-sensitive preamplifier. The feedback
resistor.
Cfb 1fF

• To avoid ballistic deficit Rfb Cfb gt ?tdet30ns
• Rfb gt 30MO

Rfb 80MO
Qdet
U(t)
Idet(t) ?tdet 30ns
Cpar 30fF
A140
Classic F.Krummenacher charge sensitive
preamplifier realizes large Rfb and compensates
for the detector leakage current. !!! Cint ? 8
in order to avoid differentiation of the input
signal.
There is no need to compensate for the
detector leakage in GOSSIPO chip. !!! Cint is
not needed in this preamplifier and IpIb.
Rfb 1/gmM11/gmM2 80M? ,where gm is
common-source transconductance of transistor.
Ib1nA
Ib1nA
M2
M1
2Ip
Silicon sensor
Cfb
Cfb
Ileak
Output
Input
Output
Ip
Ileak Ip
IpIb1nA
Cint
13
The charge-sensitive preamplifier.
Channel-to-channel variation of the DC offset at
the output.

Vdd1.2V
UoutDC varies from channel to channel. Three
source of mismatch are in the design
M10
M8
M9
Vbias3
Ibias22nA
M2
M1
1. Mismatch in the diffrential pair
M1 vs M2 s(dVg)v2(sTM1 )2 (sßM1IdM1/gmM1)2
v2sTM1
Ibias31nA
Vbias2
Cfb 1fF
OPAMP

• Mismatch in the current mirrors M10 vs M8,M9
• sIdM8 IdM9- IdM10- /IdM8 IdM9(sßM10 )2
  (s TM10gmM10/IdM10)2 s TM10 gmM10/IdM10

M3
Output
K127
A (jw)
Input
Ibias30.2uA
Vbias1
Ib1nA
Ibias41uA
3. Mismatch in the current mirrors M5 vs M4
s(dIdM5/IdM5)v 2(sßM5 )2 (s TM5gmM5/IdM5)2
v 2gmM5/IdM5s TM5

M6
M7
M4
M5
Standard deviation of the statistical variations
of UoutDC s(dUoutDC)v (v2sTM1)2 (2v2 s
TM5gmM5/gmM1)2 (s TM10gmM10/gmM1)2
Monte-Carlo simulations in Cadence give
s(dUoutDC) 20mV (170e) .

14
The charge-sensitive preamplifier. The OPAMP.

Cfb 1fF
Rfb 80MO
Qdet
U(t)
Idet(t)
Cpar 30fF
OPAMP
The OPAMP. A(jw)gmT75/gdsT75(gdsT73/gmT73)gdsT
77jwC 140/(1jw14ns) gm is common-source
transconductance of transistor. gds is
common-source output conductance of transistor C
is total parasitic capacitance at the output.
15
The charge-sensitive preamplifier. Real signal
response and stability.

Cfb 1fF
Rfb 80MO
Qdet
U(t)
Idet(t)
Cpar 30fF
OPAMP
Peaking time 44ns
Phase-to-frequency response
Amplitude 52mV
Decay of the signal is proportional to
exp(-t/80ns)
Output signal
Phase margin 62º
Input signal 438e 70aC
Magnitude-to-frequency response
30ns
Unity gain line
Real signal response of the preamplifier.
Phase margin of the preamplifier.
16
Table1.
The charge-sensitive preamplifier. Main
specifications.

Cfb 1fF
Rfb 80MO
Qdet
U(t)
Idet(t)
Cpar 30fF
OPAMP
Radius of the input pad
Parasitic capacitance at the input of the
preamplifier
Charge sensitivity
Input referred noise (Affirma SPECTRE simulation)
Input referred noise (hand calculation of serial
thermal noise )
Peaking time of the output signal when it is a
d-response.
Peaking time of the output signal when it is the
response to the real signal
Channel-to-channel variation of the DC offset at
the output.
Power dissipation
17
Conversion to digital signal. Current
comparator.(H.Traff 1992).

Low
T1
Ithr
Uout
-A
Uout-
Iin
High
T2
Uout - Uout-
VtT2200mV
High
Iin - Ithr
Low
VtT1200mV
Ambiguity zone 30nA !!!
18
Design of the Current comparator as a
current-to-voltage converter.

Gainopen loop gmT3 / gdsT3 53 (High state)

18 (Low state)
T4
Vbias
Vt200mV
T1
Vt200mV gm1.6u
33
Uout
T3
Vt400mV
130nA
Degradation of the output impedance of T3 in Low
state causes drop of the open loop gain.
Iin
T2
Vt200mV gm1.6u
Uout-
UDC300mV
Zin
Ambiguity state. Iin 0nA.
500kO
Zin1/ gmT1,T2 Gainopen loop
Low state. Iin - 60nA
40kO
High state. Iin 60nA
14kO
Freg,
10MHz
19
Interface to the Current comparator. Design of
the ac-coupled voltage-to-current converter.

Charge sensitive Preamplifier is
a Current-to-voltage converter
Voltage-to-current converter
Current Comparator is a current-to-voltage
converter
LVDS Driver
voltage
current
Vbias2
Ibias1200nA
Cc200fF
M1
M2
1. Differentiation time constant of the
AC-coupling Cc Ron 200usec gtgt
signal duration time. 2. Gain Iout/Uin 0.5
gmT1 90nA/52mV (438e). 3. Channel-to-channel
Gain variation s(dGain/Gain)
10 (44e). 4. Output impedance 1/ gdsT3 100
MO. 5. Channel-to-channel variation of the
output DC current s(dIoutDC)
24nA (120e).
Uin
Vbias3
Ron1GO
M4
Ithr42nA
Vbias1
Iout
M3
20
Design of the complete comparator with DC
hysteresis.
Charge sensitive Preamplifier is
a Current-to-voltage converter
Voltage-to-current converter
Current Comparator is a current-to-voltage
converter
LVDS Driver
voltage
current
voltage
Hysteresis or positive feedback allows to avoid
too short pulses and double pulses at the output
of the comparator. U(THRup )-U(THRdown)
15nA(73e) snoise 0.2 U(THRup) 75e
snoise
THRup
THRdown
Vbias2
Uin
Vbias3
Ithr42nA
Vbias
33
Uout
Vbias1
Iout
Ithr15nA
130nA
Uout-
UDC300mV
21
Design of the LVDS output driver.

Charge sensitive Preamplifier is
a Current-to-voltage converter
Voltage-to-current converter
Current Comparator is a current-to-voltage
converter
LVDS Driver
voltage
current
voltage
voltage
The Low Voltage Differential Driver (LVDS)
delivers the digital signals to the external low
impedance load.
Ibias85uA
Ibias21uA
?U 100mV
?U 55mV
Uin
Uout-
Uout
Uin-
R31kO
Rl7kO
R27kO
R41kO
Cpar 8pF
Cpar 8pF
22
The signals in the design .

Time-walk at the output of the LVDS driver as a
function of the signal amplitude (Amp).
Threshold 350e.
Input current signal coming from pixel pad
Amp9000e
Amp1800e
Amp900e
Output of the preamplifier
Amp438e
Threshold
Amp350e
Output of the current comparator.
?T45ns
Output of the LVDS driver.
23
Design of the bias circuit.

A filter is needed to suppress common bus
noise. A 1th order low-pass filter with cut-off
frequency fcut-off 1/2p Ron Cncap 16kHz
Ron1GO W/L0.16u/24u Vgs38mW Vthr250mV
T1
Cncap 10fF (11fF/um2 )
T2
R1
Vgs38mW
T3
Control determines current (voltage drop over R1).
T4
Channel-to-channel spread of the output
impedances T1T4 is given as follows s(d(gds)/gds
) s(dVt) /nFt 15
24
Conclusion and plans. . There will be no silicon
sensor on the GOSSIPO chip due to a novel concept
of the particle detection that allows to
circumvent major constrains related to that. .
Low input parasitic capacitance and no need for
the detector leakage current compensation at the
input are the reasons to expect an outstanding
performance of the design. . Design of the
GOSSIPO chip is in progress on the basis of the
potentialities of the 0.13um CMOS . The following
specification have been found feasible so far
a) parasitic input capacitance
10fF.30fF. b) input referred
electronic noise snoise 70e (corresponds to
THR350e). c) d-response peaking
time 36ns , real signal response peaking time
52ns . d) analog power dissipation
1.7uW/channel for 1.2V supply (without LVDS
driver). e) channel-to-channel
threshold dispersion sTHR 140e. . There will be
4 individual channels on the chip. Each channel
will be equipped with a charge-sensitive
preamplifier ac-coupled to a current comparator
with DC hysteresis and a LVDS driver. . Vertical
Parallel Plate (VPP) or fringe capacitor seems to
be suitable for injection of the test signal.
The VPP-based capacitance is taken to implement
the feedback capacitance in the preamplifier. . A
dedicated circuit on the chip will provide all
the channels with bias voltages (currents). .
Low-pass filters have been added to each channel
to avoid common bus noise. . We look to submit
this prototype within CERN organized MPW run in
December 2005.