Interrupt driven I/O

1
Interrupt driven I/O
2
MIPS RISC Exception Mechanism

• The processor operates in
• user mode
• kernel mode
• Access to additional set of registers and to
  user-mode restricted memory space available when
  the processor operates in kernel mode.
• The MIPS RISC architecture includes the notion of
  co-processors. If the floating point co-processor
  is not present it can be emulated by a software.

3
Co-processors

• The co-processor C1 execute floating point
  instructions and contain floating point
  registers.
• If the coprocessor C1 does not exist and an
  instruction specifies a floating point register,
  a trap occurs. The exception handler can identify
  the operation specified and may invoke software
  routines to achieve the effect of the specified
  operation.
• The co-processor C0 is always present and
  contains registers useful for handling exceptions
  but is not accessible in user mode. C0 includes
  the status register, cause register, BadVaddr,
  and EPC (exception program counter).

4
Co-processor 0
5
Cause Register

• The cause register contains information about
  pending interrupts and the kinds of exception
  that occurs.
• The contents of the cause register can be copied
  into an ordinary register and have the individual
  bits tested to determine what caused an exception
  to occur.
• mfc0 26, 13
• The above instruction moves data from coprocessor
  0 register 13(cause register) to general purpose
  register 26

6
Cause Register
7
Status Register

• The status register contains information about
  the status of features of the computer that can
  be set by the processor while in kernel mode

indicates whether the processor was in kernel
or user mode when the last exception occurred
indicates whether current status is kernel or user
8
Status Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mode Enable Mode Enable Mode Enable
Old Prev Cur
Mode 1user, 0kernel Enable 1on, 0off
9
EPC (exception program counter)

• Contains the address of the instruction that was
  executing when the exception was generated.
• Control can be made to return to this location to
  continue the program.
• The contents of EPC can be transferred to a
  general register via the following instruction
• mfc0 Rt, 14

10
Exception Handler

• The MIPS R32 architecture fixes the starting
  address of the exception handler to 0x8000 0180.
• A jump table consists of a list of procedure
  addresses to be called to deal with the various
  exception conditions.
• In an interrupt, the PC had already been
  incremented and EPC would contain the correct
  return address.
• In a syscall, the EPC contains the address of the
  syscall itself, thus the exception handler must
  first increment the return address by one before
  the return.

11
Handling an exception

• An exception has occurred. What happens?
• The hardware
• copies PC into EPC (14 on cop0) and puts correct
  code into Cause Reg (13 on cop0)
• Sets PC to 0x80000180, process
• enters kernel mode
• Exception handler (software)
• Checks cause register (bits 5 to 2 of 13 in cp0)
• jumps to exception service routine for the
  current exception

12
OS Issues

• When an interrupt is serviced the processor must
  be able to execute without being interrupted. It
  must have the capability of temporarily disabling
  the interrupt atomically.
• If an interrupt occurs while an interrupt service
  is ongoing, it is simply deferred and considered
  a pending interrupt. It is serviced after the
  current request terminates.
• The MIPS RISC architecture does not allow user
  programs to access beyond 0x8000 0000 (the upper
  half of the memory). The exception handler is in
  this part of memory and only executed in kernel
  mode.

13
OS Issues

• Changing the mode back to the mode before the
  exception occurs is accomplished via the
  instruction eret
• Old ? Previous ? Current
• The mode information is stored in the Status
  Register and can only be written in the kernel
  mode. It can be read in user mode.

14
OS Issues

• Enabling and disabling of interrupts can be done
  either by applying an interrupt mask (IPM) to
  bits 10-15, or the enable bit of the Status
  Register.
• The execution of eret enables interrupts

15
OS Issues

• A reentrant exception handler is written such
  that it is itself interruptible.
• Interrupts and traps are assigned priorities.
• A check is made for pending interrupt requests
  after every instruction.
• If there is a pending interrupt request, the
  priority is checked. If it has a higher priority
  than the currently running code, it serviced
  first, otherwise it is ignored.

16
Enabling interrupts

• By default, interrupts are disabled in SPIM
• To use respond to interrupts, a program must
• Enable interrupts
• Status register
• Enable the interrupt for the specific device
• Status register
• Instruction the device controller to cause
  interrupts
• Device control memory mapped address

17
Software Interrupt Driven I/O

• Exceptions come in two varieties
• Interrupts are generated by hardware
• I/O device
• Clock
• Power down
• Traps are generated by code execution
• Division by zero
• Illegal memory address
• System call

18
Interrupt driven I/O structure

• Our programs have all run in kernel mode only
• Code to service an interrupt must be called from
  location 0x8000180
• We must return to the address at which the
  interrupt occurred

kernel
0xffffffff 0x80000080 0x80000000 0x1000000
0 0x00400000 0x00000000
stack
code
19
Interrupt driven I/O structure

• A queue is needed for both input and output
• Input
• Characters are added when a keyboard interrupt
  occurs
• Characters are removed when the input function is
  called
• Output
• Characters are removed when a display interrupt
  occurs
• Characters are added when a keyboard interrupt
  occurs
• Echoing
• Characters are added when the output function is
  called
• The output function must initiate the first
  display handler call
• Thereafter, interrupts occur when the display
  becomes ready

20
Interrupt driven I/O structure
User data
input function (syscall 8)
input
output function (syscall 4)
echo
output
21
Protecting the buffers

• The input and output buffers may be modified in
  response to an interrupt
• This could occur while the CPU is in the middle
  of executing user code which reads from the input
  buffer or writes to the output buffer
• To prevent this destructive concurrent access, we
  must disable interrupt while accessing the
  buffers
• Explicitly and status with 0xfffffffe
• Implement I/O functions as system calls