Digital Radio SoC Lab

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Digital Radio SoC Lab

• 2004 Spring

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Timing Fundamentals

• Content
• Notation summary
• Propagation delay
• Rise and Fall time
• Contamination delay
• Combinational logic in series
• D-latch
• Edge triggered flip-flop
• Flip-Flop timing
• References

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Timing Fundamentals

• Notation summary
• rise time
• fall time
• propagation delay
• propagation delay from high to low
• propagation delay from low to high
• contamination delay
• A? B??? propagation delay
• A? B??? contamination delay
• or setup time
• hold time
• propagation delay? ?? ? path? delay
• FF1 (? ?? Flip-Flop)? propagation
  delay
• clock period
• maximum clock frequency
• resolution time

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Timing Fundamentals

• Propagation Delay
• Valid input? ???? valid output? ?? ? ?? delay?
  Upper bound
• ?? input-output path? valid input?? valid output
  ?? transition??? ??? time delay ? ?? ? delay
• ? circuit? ???? transistor?? turn on/off
  ??? ??? ???

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Timing Fundamentals

• Propagation Delay (Cont.)
• Assumption
• Input? ideal digital signal ?
• Contamination delay 0

Average Propagation Delay
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Timing Fundamentals

• Propagation Delay (Cont.)

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Timing Fundamentals

• Propagation Delay (Cont.)

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Timing Fundamentals

• Propagation Delay (Cont.)
• Sedra/Smith, Microelectronic Circuits, chapter 5
• When
• - where
• When

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Timing Fundamentals

• Propagation Delay (Cont.)
• Falling Case
• n-MOS ON saturation
• P-MOS OFF linear

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Timing Fundamentals

• Propagation Delay (Cont.)
• Falling Case
• When

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Timing Fundamentals

• Propagation Delay (Cont.)
• Falling Case
• When

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Timing Fundamentals

• Propagation Delay (Cont.)
• Falling Case

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Timing Fundamentals

• Propagation Delay (Cont.)
• Falling Case

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Timing Fundamentals

• Propagation Delay (Cont.)
• Falling Case
• Example

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Timing Fundamentals

• Propagation Delay (Cont.)
• Falling Case
• Example (Cont.)
• - (i)
• - (ii)

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Timing Fundamentals

• Rise and Fall time
• ? ? time constant
• Rise time Invalid low?? valid high?
  transition?? time
• Fall time Invalid high?? valid low?
  transition?? time
• (ex) inverter

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Timing Fundamentals

• Rise and Fall Time (Cont.)

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Timing Fundamentals

• Contamination delay
• Invalid input? ???? invalid output? ?? ? ??
  delay? lower bound
• Invalid input? propagate??? ??? ????, ? ??? ??
  valid? output?
• ?? input-output path? invalid input?? invalid
  output?? transition? ???? ? ??? time delay ? ??
  ?? delay
• Additional optional timing spec.
• ?? ??? ?? spec.??? register ??? timing margin? ??
  ??? spec.
• Spec? ?? ?? ?? ?? ??? ???? 0?? ???
• ?? ?? ?? ?? ??? ??? ? ??

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Timing Fundamentals

• Contamination delay (Cont.)
• Combinational logic in series Timing
  uncertainty ??? ?? 2
• Combinational logic circuit? cascade??
  propagation delay? ??? element delay? ?? ?
  (contamination delay? ????)
• Shaded region? uncertainty ??? (unstable or
  unknown state)
• Contamination delay lt propagation delay

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Timing Fundamentals

• Contamination delay (Cont.)
• (ex 1) Timing analysis Cascaded inverter

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Timing Fundamentals

• Contamination delay (Cont.)
• (ex 2) Timing analysis Contamination delay
  Propagation delay
• NAND gate? ?
  ? ??? ?? ?, ?? logic? timing ??
• Timing analysis
• ? input?? output?? ???? ?? path ? minimum
  cumulative contamination delay 1ns 1ns 2ns
• ? input?? output?? ???? ?? path ? maximum
  cumulative propagation delay 4ns 4ns 4ns
  12ns

NAND
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Timing Fundamentals

• Contamination delay (Cont.)
• (ex 2) Timing analysis Contamination delay
  Propagation delay (Cont.)

Case 1
Case 2
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Timing Fundamentals

• Contamination delay (Cont.)
• (ex 2) Timing analysis Contamination delay
  Propagation delay (Cont.)
• NAND gate? ?
  ? ??? ?? ?, ?? logic? timing ??
• - Worst case? ???? ?? contamination delay?
  minimum ??? ??, propagation delay? maximum??? ??

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Timing Fundamentals

• Contamination delay (Cont.)
• Contamination delay? ???? ??

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Timing Fundamentals

• D latch

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Timing Fundamentals

• D latch
• Interval prior to G transition for which D must
  be stable valid
• Interval following G transition for which D must
  be stable valid

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Timing Fundamentals

• Edge-triggered Flip Flop

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Timing Fundamentals

• Edge-triggered Flip Flop
• Only one latch transparent at any time
• Master (latch 1) closed when slave (latch 2) is
  open
• Slave closed when master is open
• Q only changes shortly after 0 ? 1 transition of
  CLK
• Flip Flop appears to be triggered by rising edge
  of CLK

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Timing Fundamentals

• Flip-Flop Timing
• Setup time
• Clock pulse? triggering edge ??? input? ?? ????
  ????? ?? ???? time interval
• Hold time
• Clock pulse? triggering edge ??? input? ?? ????
  ????? ?? ???? time interval

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Timing Fundamentals

• Flip-Flop Timing (Cont.)

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Timing Fundamentals

• Flip-Flop Timing (Cont.)
• (ex) Timing analysis setup time hold time
• Clock period 25 ns ??, clock skew? ??? ???
• Timing violation ?? ?? ?? Flip-Flop? maximum
  setup time? hold time
• Maximum setup time
  25 6 max(11,9) 8ns
• Maximum hold time
  2 min(4,5) 6ns

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Timing Fundamentals
NAND gate

• Metastability

SR latch truth table
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Timing Fundamentals

• Metastability (Cont.)
• Reason of Metastability
• Setup or hold time violation
• Asynchronous input signal
• How long does it stay in metastability?
• Its unpredictable
• Thermal or induced noise? ?? metastable state??
  ??? 0 or 1? stable state? ??

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Timing Fundamentals

• Metastability (Cont.)
• Synchronizer operation
• If the asynch. Input doesnt meet a stable
  condition during setup time,
• itll be clocked through with a latency of one
  clock cycle
• Otherwise, FF1 may enter metastability
• If metastability is resolved in less than one
  clock - FF2 setup time,
• FF2 will have a stable input

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Timing Fundamentals

• References
• 1 MIT Computation structure lecture note,
  chapter 3 Gate
• 2 William J. Dally, Digital system
  engineering, CAMBRIDGE university press, chapter
  12 Timing Circuits