Fully Parallel Learning Neural Network Chip for Real-time Control

1
Fully Parallel Learning Neural Network Chip for
Real-time Control

• Advisor Dr. Martin Brooke
• Students Jin Liu and Bortecene Terlemez

2
Overview

• Simulation Results Review
• Recent Experimental Results
• Next Generation Hardware
• Plans

3
Simulation Results Review

• Simulated Neural Net and Combustion
• Multi-frequency Results
• Parameter Variation Results
• Added Noise Results

4
Simulation Setup
Unstable
x
u
Combustion Model
Delay 1.5 ms
error
error
Delay line
Software Simulation of
Neural Network Chip
5
Two frequency Results
f400Hz f700Hz
b?
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Parameter Variation Results
f400-600Hz ?0-0.008 B1-100
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10 Added Noise Results
f400Hz ?0.005 B1
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Experimental Results

• NN Chip Control Simulated Combustion
• Hardware Control of Combustion Simulation
• Hardware Control Results

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Hardware Control of Combustion Simulation Setup
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Hardware Control of Combustion Simulation Control
Loop
x
u

w 2p(400Hz)
z 0.0
b 1
Delay 1.5ms
error
2.5 ms
8 taps
Delay line
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Hardware Control Results
w 2p(400Hz)
z 0.0
b 1
12
Hardware Control Results - Continued
w 2p(400Hz)
z 0.0
b 1
13
Hardware Control Results - Continued
w 2p(400Hz)
z 0.0
b 1
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Next Generation Hardware

• More Powerful
• New Technology
• Improved Algorithms

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More Powerful

• 720 Parallel Weights (720,000 MIPS Throughput)
• Two Layers
• 30 Inputs Each
• 20 and 4 Outputs
• 2 Errors for First Layer

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New Technology
New Chip 0.35-mm
Old Chip 2.0-mm
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Improved Algorithms

• Controllable Learning Step Size
• Adaptive Error Feedback

18
Plans

• Two layer Hardware tests
• Acoustic Oscillation Suppression
• Real Combustion Control
• Test of New Chip
• Third Generation Chip

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Acoustic Oscillation Setup

• Forced Air Oscillations
• Hardware Chip and Real Plant
• Real-Time Issues
• latency vs. throughput
• real-time operating system
• Schedule
• February finish build
• March Testing underway

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Acoustic Oscillation Setup
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Real Combustion Control

• Schedule
• April finalize control setup
• May duplicate setup for AE
• June Start?

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Test of New Chip

• Goals
• more weights, bigger networks
• multi-output/input control
• Schedule
• March chip goes to fabrication
• July chip ready for tests

23
Design of Third Generation Chip

• Goals
• static weights for long term learning
• many more weights (10,000-100,000)
• Schedule
• 99 develop weights and learning rules
• 00 first silicon