ACOE361

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ACOE361 Digital Systems Design
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Useful information

• Instructor Lecturer K. Tatas
• Office hours Mo5, Tu3, We6-8, Fri5
• Prerequisites ACOE201 (ACOE161)
• Teaching 4 periods/week
• 3 Lecture
• 1 Lab
• ECTS 6 (6x25 150h)
• Enrollment key ACOE361_FALL12

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Course Objectives

• Introduce students to advanced topics in Digital
  System Design
• Synchronous Sequential Circuit Design using
  State/ASM diagrams
• Hardware Description Languages
• EDA tools
• ASIC/FPGA implementation technologies

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Course Outcomes

• Understand the digital system design flow
• Understand the role of EDA tools in ASIC/VLSI
  design
• Be familiar with ASIC, PLD, FPGA technologies
• Design hazard-free synchronous and asynchronous
  digital systems using ASM
• Implement Mealy and Moore ASMs using PROMs,
  multiplexers, PLDs, FPLAs, FPGAs
• Become fluent in VHDL
• Understand Verification concepts and design
  testbenches

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Course Description

• Digital Systems Design - ASMs
• ASMs, Mealy and Moore machines. ASM charts.
• VE? minimization.
• IFL/OFL minimization and implementation.
• State machine implementation using PROMs and
  multiplexers.
• Finite state machine implementation using FPLAs.
• Timing. Glitch minimization techniques.
• Asynchronous input systems. Asynchronous input
  synchronization

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Course Description

• ASIC architectures and Implementation Options
• Synthesis and EDA tools for ASIC and FPGA
  implementation
• Semi-custom / full custom ASICs.
• Gate Array, Standard Cell, Full Custom,
  CMOS/BI-CMOS technologies
• PLDs and FPGAs.

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Course Description

• VHDL
• Top-Down Design.
• File organization.
• Entity and Architecture.
• Structural and Behavioural Description.
• VHDL Primitives.
• Signal Queues and Delta times.
• Concurrent and sequential statements.
• Procedures and functions.
• Packages and design for reuse.

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Course Description

• Verification
• Basic verification methodology
• Testbenches
• directed and constrained-random testing
• self-checking testbenches

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Course Description

• EDA Tools
• Synthesis
• VHDL Synthesis coding guidelines
• Synthesis optimization options
• Implementation

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Course Outline

• Week 1
• Lecture 1 Digital Revision
• Lecture 2 FSMs
• Week 2
• Lecture 1 Sequential circuits Examples
• Lecture 2 ASMs
• Week 3
• Lecture 1 Synchronous Design
• Lecture 2 Examples
• Week 4
• Lecture 1 Test 1
• Lecture 2 Design Flow
• Week 5
• Lecture 1 VHDL
• Lecture 2 Lab 1
• Week 6
• Lecture 1 VHDL
• Lecture 2 Lab 2
• Week 7

• Week 8
• Lecture 1 VHDL
• Lecture 2 Lab 4
• Week 9
• Lecture 1 Verification
• Lecture 2 Lab 5
• Week 10
• Lecture 1 Logic Synthesis
• Lecture 2 Lab 6
• Week 11
• Lecture 1 Test 2
• Lecture 2 Assignment/Group project
• Week 12
• Lecture 1 Assignment/Group project review Case
  study
• Lecture 2 Lab 7
• Week 13
• Lecture 1 Assignment/Group project assessment
• Lecture 2 Revision

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Course Evaluation

• Final exam 40
• Coursework 60
• Test 20
• Assignment/Group project 20
• Laboratory work 20

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Textbooks and References

• J. F. Wakerly, Digital Design Principles and
  Practices, Prentice Hall, 2003.
• V. Pedroni, The students guide to VHDL, Morgan
  Kaufmann, 1998.
• M. Mano, Digital Design, Prentice Hall, 2002.
• T. Floyd, Digital Fundamentals, Prentice Hall,
  2002.

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Basic Logic Gates
Logic Function
Gate Symbol
Logic Expression
Truth Table
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Basic Logic Gates with Inverted Outputs
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Revision on MSI Devices
M. Mano C. Kime Logic and Computer Design
Fundamentals (Chapter 5)
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MSI Devices

• Medium Scale Integration (MSI) devices are
  digital devices that are build using a few tens
  to hundreds of logic gates.
• MSI devices are used as discrete devices packed
  in a single Integrated Circuit (IC), or as
  building blocks for other, more complex devices
  such as memory devices or microprocessors.
• Some typical MSI devices are the following
• Encoders and Decoders
• Multiplexers and Demultiplexers
• Full Adders
• Latches and flip flops
• Registers and Counters

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Examples of MSI Devices
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Decoders

• A decoder is a combinational digital circuit with
  a number of inputs n and a number of outputs
  m, where m 2n
• Only one of the outputs is enabled at a time. The
  output enabled is the one specified by the binary
  number formed at the inputs of the decoder.
• On the circuit below, the inputs of the decoder
  are connected on three switches, forming the
  number 5 (101)2, thus only the lamp 5 will be
  ON

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2 to 4 Line Decoder
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3 to 8 Line Decoder
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Multiplexers

• A multiplexer is a device that has a number of
  data inputs m, and number of control inputs n
  and one output, such that m2n. The output has
  always the same value as the data input specified
  by the binary number at the control inputs.
• The rotary switch (selector) shown in figure (a)
  below, is equivalent to a 4-to-1 multiplexer.
• The sliding switch shown in figure (b) below, is
  equivalent to an 8-to-1 multiplexer.

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Internal structure of a 2-to-1 multiplexer.

• The design of a 2-to-1 multiplexer is shown
  below.
• If S0 then the output Y has the same value as
  the input I0
• If S1 then the output Y has the same value as
  the input I1

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1-bit Full Adder
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4-bit Full Adder (Ripple-Carry Adder)

• To obtain a 4-bit full adder we cascade four
  1-bit full adders, by connecting the Carry Out
  bit of bit column M to the Carry In of the bit
  column M1, as shown below. The Carry In of the
  Least Significant column is set to zero.

• Example Find the bit values of the outputs
  Cout,S3..S0 of the full adder shown below, if
  A3..A0 1011 and B3..B0 0111.

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Magnitude Comparator
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The D Edge Triggered Flip Flop

• The D edge triggered flip flop can be obtained by
  connecting the J with the K inputs of a JK flip
  through an inverter as shown below. The D edge
  trigger can also be obtained by connecting the S
  with the R inputs of a SR edge triggered flip
  flop through an inverter.

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The Toggle (T) Edge Triggered Flip Flop

• The T edge triggered flip flop can be obtained by
  connecting the J with the K inputs of a JK flip
  directly. When T is zero then both J and K are
  zero and the Q output does not change. When T is
  one then both J and K are one and the Q output
  will change to the opposite state, or toggle.

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D and T Edge Triggered Flip Flops - Example

• Complete the timing diagrams for
• Positive Edge Triggered D Flip Flop
• Positive Edge Triggered T Flip Flop
• Negative Edge Triggered T Flip Flop
• Negative Edge Triggered D Flip Flop

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Flip Flops with asynchronous inputs (Preset and
Clear)

• Two extra inputs are often found on flip flops,
  that either clear or preset the output. These
  inputs are effective at any time, thus are called
  asynchronous. If the Clear is at logic 0 then the
  output is forced to 0, irrespective of the other
  normal inputs. If the Preset is at logic 0 then
  the output is forced to 1, irrespective of the
  other normal inputs. The preset and the clear
  inputs can not be 0 simultaneously. In the Preset
  and Clear are both 1 then the flip flop behaves
  according to its normal truth table.

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JK Flip Flop With Preset and Clear- Example

• Complete the timing diagrams for
• Positive Edge Triggered JK Flip Flop
• Negative Edge Triggered JK Flip Flop.
• Assume that for both cases the Q output is
  initially at logic zero.

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Sequential circuit example 1