Design Techniques for Radiation Hardened

1
Design Techniques for Radiation Hardened Phase
Locked Loops
Anantha Nag Nemmani, Martin Vandepas, Kerem Ok,
Kartikeya Mayaram and Un-Ku Moon Oregon State
University Electrical Engineering and Computer
Science
2005 MAPLD International Conference ? Ronald
Reagan Building and International Trade
Center Washington, D.C. ? September 7-9, 2005
Effects
Single Event Effects (SEE)
Total Ionization Dose (TID)
Effect on Phase Locked Loops (PLLs)
SEE on PLLs

• VCO tuning curves shift
• Change in nominal frequency and VCO gain
• Change in chargepump current
• Loop parameters changed as a result
• Loop transfer function altered

• Accumulation of charge in gate oxide
• Vth NMOS ? Vth PMOS ?

• Transient error currents
• Modelled as sum of exponential current sources

Digital PLL
Tuning curves of Lee/Kim Ring oscillator before
and after radiation.
SEE on last stage of frequency divider
SEE on control node
Digital Loop Filter
Time-to-digital converter
Digitally controlled analog oscillator

• Digitally controlled analog oscillator (DCAO)
• Time-to-digital converter (TDC)
• Digital loop filter

• Exponential delay chain
• Latches
• Sign detection
• Pseudo-thermometor encoder

• Lee/Kim delay cell
• Fine/Coarse tuning

• Fine tuning current DAC
• 6 fine bits 6 coarse bits

• Type II loop filter

Analysis
Operation of a TDC
Analysis Verification
DCAO resolution
1. DCAO
Openloop gain
For optimum performance Phase margin - FM
Incremental phase accumulated
2. Phase detector
3. Loop filter
CPPLL Analogy
Response to frequency step at the input.
Simulink Agrees with mathematical model
Radiation Hardening
Self-Calibration
Layout
Redundancy Majority Voting
Single Event Hardening

• Loop parameters
• fLSB dT Process dependent
• Gn, a ß Digital constants
• Loop dynamics are dependent only dependent on
• Self calibration
• Calibrate Kdig to the desired value

Accumulator
Time-to-digital converter
Frequency Divider
MAPLD 2005/228