Embedded Systems Hardware:

1

• Embedded Systems Hardware
• Storage Elements
• Finite State Machines
• Sequential Logic

2
fig_03_08
Finite state machine (FSM) High-level
view Moore machine output is a function of the
present state only Mealy machine output is a
function of the present stare and the inputs
fig_03_08
3
fig_03_15
fig_03_15
fig_03_16
Verilogshift registers behavioral and
structural (porpower on reset)
4
fig_03_20
Linear feedback shift register (for providing
random numbers, e.g.) Note pullUp needed to
prevent floating Reset pin on D flipflops What
goes in Feedback Logic block? CHOICE IS NOT
ARBITRARY, DEPENDS ON PROPERTIES OF POLYNOMIALS
OVER THE FINITE FIELD 0,1,,xor, (e.g., 110).
Table of correct values for an n-bit register is
given in Appendix of Hamblen.
fig_03_20, 3_21, 3_22
5
fig_03_23
Dividers slow clock down, e.g. Simple
divide-by-2 example
fig_03_23,3_24
6
fig_03_25
Example Asynchronous divide-by-4
counter asynchronous 2-bit binary upcounter
ripple counter Note asynchronous because
flip-flops are changed by different signals Note
if 1st stage output appears at time t0 m, nth
stage output appears at time t0 nm so this
configuration is good for dividing the signal but
using it as a ripple counter is prone to static
and dynamic hazards
Both outputs change
fig_03_25, 03_26, 03_27
7
fig_03_29
Synchronous dividers and counters
(preferred) Example 2-bit binary
upcounter Inputs DA not A DB A xor B
fig_03_28, 03_29
8
fig_03_30
Johnson counter (2-bit) shift register
feedback input often used in embedded
applications states for a Gray code thus states
can be decoded using combinational logic there
will not be any race conditions or hazards
fig_03_30, 03_31, 03_32, 03_33
9
fig_03_34
3-stage Johnson counter --Output is Gray
sequenceno decoding spikes --not all 23 (2n)
states are legalperiod is 2n (here
236) --unused states are illegal must prevent
circuit from ever going into these states
fig_03_34
10

• Making actual working circuits
• Must consider
• --timing in latches and flip-flops
• --clock distribution
• --how to test sequential circuits (with n
  flip-flops, there are potentially 2n states, a
  large number access to individual flipflops for
  testing must also be carefully planned)

11
fig_03_36
Timing in latches and flip-flops Setup time
how long must inputs be present and stable before
gate or clock changes state? Hold time how long
must input remain stable after the gate or clock
has changed state?
fig_03_36, 03_37
Metastable oscillations can occur if timing is
not correct
Setup and hold times for a gated latch enabled by
a logical 1 on the gate
12
fig_03_38
Example positive edge triggered FF 50 point of
each signal
fig_03_38
13
fig_03_39
Propagation delay minimum, typical, maximum
values--with respect to causative edge of
clock Latch must also specify delay when
gate is enabled
fig_03_39, 03-40
14
fig_03_41
Timing margins example increasing frequency
for 2-stage Johnson counter output from either
FF is 00110011. assume tPDLH
5-16ns tPDLH 7-18ns tsu 16ns
fig_03_41, 03_42
15

• Case 1 L to H transition of QA
• Clock period tPDLH tsu slack0 ? tPDLH tsu
  
• If tPDLH is max,
• Frequency Fmax 1/ 5 16) 10-9sec 48MHz
• If it is min, Fmax 31.3 MHz
• Case 2 H to L transition
• Similar calculations give Fmax 43.5 MHz or
  29.4 MHz
• Conclusion Fmax cannot be larger than 29.4 MHz
  to get correct behavior

16

• Clocks and clock distribution
• --frequency and frequency range
• --rise times and fall times
• --stability
• --precision

17
fig_03_43
Clocks and clock distribution Lower frequency
than input can use divider circuit above Higher
frequncy can use phase locked loop
fig_03_43
18
fig_03_44
Selecting portion of clock rate multiplier
fig_03_44
19
fig_03_46
Note delays can accumulate
fig_03_46
20
fig_03_47
Clock design and distribution Need
precision Need to decide on number of
phases Distribution need to be careful about
delays Example H-tree / buffers
fig_03_47
21
fig_03_48
Testing Scan path is basic tool
fig_03_48
22
fig_03_56
Testing fsms Real-world fsms are weakly
connected, i.e., we cant get from any state S1
to any state S2 (but we could if we treat the
transition diagram as an UNDIRECTED
graph) Strongly connected we can get from a
state S initial to any state Sj sequence of
inputs which permits this is called a transfer
sequence Homing sequence produce a unique
destination state after it is applied Inputs I
test Ihoming Itransfer Finding a fault
requires a Distinguishing sequence
Example Strongly connected Weakly
connected
fig_03_56
23
fig_03_57
Basic testing setup
fig_03_57
24
fig_03_58
fig_03_58
25
fig_03_59
Example machine specified by table
below Successor tree
fig_03_59
26
fig_03_63
Example recognize 1010
fig_03_63
27
fig_03_65
Scan path
fig_03_65
28
fig_03_66
Standardized boundary scan architecture
Architecture and unit under test
fig_03_66