PicoBlaze

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PicoBlaze MicroBlaze

• Ernest Jamro
• Dep. Of Electronics
• AGH University of
• Science and Technology

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MicroBlaze

• 32 bit soft-processor
• 32 bit instructions
• 32 registers
• Independent data and instruction buses
• Different bus standards
• - PLB (Processor Local Bus)
• - AXI (Advanced eXtensible Interface)
• - LMB (Local Memory Bus)
• - FSL (Fast Simplex Link)

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MicroBlaze Block Diagram
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Different Bus Configurations
LMB AXI / PLB Complexity simply complex
Local/glonal local global Master 1 gt1
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MB bus configurations only LMB This
configuration cannot communicat with external
modules, thus should not be employed
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LMB Instructions, PLBData
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EDK Print Screen
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InstructionsLMB Data PLB LMBMB employs LMB
for instructions and memory accessand PLB/AXI
for peripheral module access
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Only one PLB/AXI bus
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Two PLB/AXI buses
Warning plb_ddr memory cannot be written (how to
initialise instruction memory)
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Two PLBs, single memory
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Without Data Cache
Manual (in C program) handling of data memory
transfer
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Example (6)The MB is booted from BRAM
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Fast Simplex Link (FSL)
32-bit single direction bus one master one slave
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Registers

• R0-R31 32x32-bit general purpose registers R0-
  always equal to 0
• PC Program counter initial value 0
• MSR (Machine State Register)

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MSR
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Instruction Format
Typu A Instruction
Typu B instruction
Example instruction ADD
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Example of Instructions
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(No Transcript)
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Pipeline Architecture
Delay Slot Instructions
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(Hard)Procesor (e.g. PowerPC in Virtex 2Pro)

• Implemented directly in silicon (ASIC
  technology)
• Employs ASIC technology (not FPGA technology) so
  this silicon area cannot be reused for other
  purposes
• Parameters are defined (ASIC) and cannot be
  changed
• Is relatively fast and consumes relatively small
  silicon area and power

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Soft-procesor (e.g. MicroBlaze)

• Employs standard FPGA logic resources
• thus the logic resources can be freed when not
  required
• Parameters can be freely defined by a user
• In comparison to the hard-processor is slower,
  consumes more silicon area and power

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MicroBlaze parameters

• Different types of buses (PLB/AXI, LMB)
• (Implement or not) cache memory, define its size
• Barrel-Shifter
• fast multiplier define the bit-width of the
  multiplier 32-bit, 64-bit
• divider
• debugger (and its parameters)
• Floating-point unit (and its parameters)
• MMU Memory Management Unit

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EDK - Ports
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EDK Addresses
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Adding IP-Cores
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IP-Core Options
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Microprocessor Hardware Specification
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8-bit soft-processor PicoBlaze

• Optimized for Xilinx Spartan-3
  architecturejust 96 slices (0.3 of an
• XC3S5000 device) and 0.5 to 1 block RAM
• 16 byte-wide general-purpose data registers
• 1K instructions of programmable on-chip program
  store, automatically loaded during
• FPGA configuration
• Byte-wide Arithmetic Logic Unit (ALU) with
  CARRY and ZERO indicator flags
• 64-byte internal scratchpad RAM
• 256 input and 256 output ports for easy
  expansion and enhancement
• Automatic 31-location CALL/RETURN stack
• Predictable performance, always two clock
  cycles per instruction, up to 200 MHz or
• 100 MIPS in a Virtex-II Pro FPGA
• Fast interrupt response worst-case 5 clock
  cycles
• Support in Spartan-6, and Virtex-6 FPGA
  architectures
• Assembler, instruction-set simulator support

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Block diagram
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Example, external multiplier
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PicoBlaze, in VHDL
processor kcpsm port map( address gt
address_signal, instruction gt instruction_signal,
port_id gt port_id_signal, write_strobe gt
write_strobe_signal, out_port gt
out_port_signal, read_strobe gt
read_strobe_signal, in_port gt in_port_signal, int
errupt gt interrupt_signal, reset gt
reset_signal, clk gt clk_signal)
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PB, assembler
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PB, data moving
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MicroBlaze cache memory

• Small cache memory is much quicker than external
  memory
• For the MB it is better to use internal BRAM
  memory (in the case when data moving is easily
  determined) than cache as BRAM as quick as cache
  memory but consumes less recourses

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cache block structureThis structure is for
tutorial-pupose only (not used in real
applications)
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Real Application
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The End
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Uproszczony przyklad dzialania
Linie adresowe a30-a31 ignorowane dane sa 4
bajtowe a24-a29 linie adresowe pamieci tag i
danych (instrukcji) a0-a23 linie adresowe
zapisywane w pamieci tag i wykorzystywane podczas
porównywania
Pamiec Tag CacheL. DanaTag Cache adr 0 0x00
0x0000 1 0x00 0x0004 2 0x00 0x0008 3 0x03 0x0
30C 4 0x03 0x0310 5 0x05 0x0514 6 0x06 0x0618 7
0x07 0x071C ...
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LMB (Local Memory Bus) Sygnaly
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LMB (odczyt i zapis)
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LMB szybki odczyt