??????? Design Verification Team

1
???????Design Verification Team

• ??? ??
• Prof. Chung-Yang (Ric) Huang
• Department of Electrical Engineering
• National Taiwan University
• 2008/02/14

2
Lab Profile

• Founded in 2004.02
• Lab info
• Office EE-II 444
• Lab EE-II 353
• PTT NTUGIEE_ric
• Website
• http//dvlab.ee.ntu.edu.tw/
• To find me
• ric_at_cc.ee.ntu.edu.tw
• ric2k1 _at_ ptt, ptt2, msn, skype, ...
• 02-3366-3644

3
Research Focus

• EDA Electronic Design Automation
• Develop algorithms and tools for circuit design
  automation and optimization
• Design implementation logic and physical
  synthesis and optimization
• Design verification assuring the correctness of
  the implementation
• Design analysis evaluating the performance and
  robustness of the design

4
What is Design Verification?
always _at_(posedge clk) begin if (rst1'b1)
cnt lt sv else if (cnt2'b00) cnt lt
2'b01 else if (cnt2'b01) cnt lt 2'b10
else if (cnt2'b10) cnt lt 2'b11 else
cnt lt sv end
for (i 0 i lt d i i2) if (y gt 3) p p
3 else q q r
Bottom line to fix as many bugs in your design
as possible
Verification takes 70 of resources in todays
IC design
5
Design verification can be...

• Very engineering!
• Simulation-based approach
• Apply input patterns and verify if outputs are
  correct
• ? But how many patterns can you try? Whats the
  ?
• If a bug is found...
• Study the waveform ? Exam the signal values ?
  Trace the code ? Fix the potential causes ? Try
  again...
• ? Do you fix the bug? Any side effect?

bugs found
???
time
6
Design verification can be...
A mathematical / logic reasoning engine is
required!!

• Very theoretical...
• Formal verification

Design Under Verification (DUV)
Check consistency
Arithmetic / Logic Model (Constraints)
Properties
7
Design verification can be...

• Defining the design methodology!!
• What is System-on-Chip (SoC)?
• What is system-level design methodology?
• ? No good / established EDA tool flow yet...
• (How can design verification play a deciding
  role?)

8
3 Research Teams

• Front-end Team
• Intelligent design debugging
• Formal-based design optimization
• Formal Engine Team
• Circuit-based Boolean Satisfiability (SAT) solver
• High-level (arithmetic) solver
• Electronics System Level (ESL) Design Team
• SoC virtual platform
• System-level EDA tools

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5 On-going Projects

• ?????????????????
• Formal Modeling and Verification of Electronics
  System Level Designs, ????
• ???????????
• Formal-Assisted Technology Dependent Logic
  Optimization, ????
• ????????????????????
• Cell Library Construction and Verification for
  LTPS-TFT Digital Circuits, ??????
• N-MoIP ?????????????? MoIP ???? SoC ??
• N-MoIP SoC Design of Advanced Multimedia-over-IP
  Handheld Device for Heterogeneous Wireless
  Network Environments, ??????SoC??
• ????????????-??????????????????????
• Combining Simulation and Formal Verification
  Techniques for Trillion-transistor-Scale
  System-on-Chip (TS-SoC), ????????

More are coming soon!!
10
?????

• ?? ?? ???? Title
• ----------------------------
• 0 ??? 2004.02 ??
• 1 ??? 2004.02 ? 3
• 2 ??? 2004.05 ? 3
• 9 ??? 2004.12 RA
• 11 ??? 2004.12 ? 2
• 13 ??? 2005.04 ? 2
• 14 ??? 2005.06 ? 3
• 15 ??? 2005.06 ? 3
• 16 ??? 2005.11 ? 2
• 17 ??? 2005.11 ? 1
• 18 ??? 2005.12 ? 2
• 19 ??? 2005.12 ? 2

• 20 ??? 2005.12 ? 2
• 21 ??? 2006.04 ? 2
• 22 ??? 2006.04 ? 2
• 23 ??? 2006.11 ? 1
• 24 ??? 2006.11 ? 1
• 25 ??? 2006.11 ? 1
• 26 ??? 2006.11 ? 1
• 27 ??? 2006.11 ? 1
• 28 ??? 2007.09 RA
• 29 ??? 2007.11 ? 0
• 30 ??? 2007.11 ? 0
• 31 ??? 2007.11 ? 0
• 32 ??? 2007.12 ? 0
• ----------------------------
• ?? NTUEE
• ?? NTUCS

?? 7, ?? 11, ???? 2, ??? 4
11
???????

• ??????? EDA, ????????...
• ??!! ????????????????.
• Best recommendation letters are for best
  students.
• ???? paper ????, ????????!
• ?? ? first author ? paper ????

12
???????

• ??????? EDA ?????...
• ??!! ????? EDA ??, ??????? ?????
• Formal verification ? research ???????
• ?????? CAD ??
• http//lads.ee.ntu.edu.tw/cad08/index.htm
• ??????????????...
• ??!! ??????????????!!
• ??, ??????

13
Potential Topics for ???

• ESL Design Methodology
• ????
• ??? EDA, ?? ???????? ??
• ??
• ???? IC design flow ????, ??? Verilog ????
• ??
• ?? SoC design methodology
• ?? SystemC (? C ??? ESL language)
• ?? QuteVP virtual platform ???
• ?? weekly ESL study group

14
Potential Topics for ???

• Formal engine (theorems and algorithms)
• ????
• ?????, ?? ???????? ??
• ??
• ?????????, ??????.
• ??
• ?? formal verification ???
• ??? SoC Verification
• ?? QuteSAT or CNF SAT engine ?????
• ?? weekly engine study group
• ???????????? paper

15
Potential Topics for ???

• Open Verilog front-end release
• ????
• ??? EDA, ?? ????? ??
• ??
• ?????? sense, ??? product release ???
• ?? Verilog ?????
• ??
• QuteRTL framework ???
• ?? QuteRTL open Verilog research framework ?
  release
• Target DAC 2008 University Booth (June, San
  Diego)
• EDA product software engineering marketing ???
• We are serious about the framework release !!
• ????????? framework ???

16
Potential Topics for ???

• Intelligent Chip (iChip) ? Automatic Learning
  Pattern Generation
• ????
• ?????????????? !!
• ??
• ?????????????????
• ??
• ?????????? iChip ??????????
• Whats the HW architecture for the intelligent
  chip?
• ?? formal verification engine ???
• ?? ???? ???
• ?? ??, ??, ?? ???
• Ideas ??????

17
Potential Topics for ???

• ??
• ? ????????????, ?????????? (??????)
• ?????????????????
• ??????? idea
• ????, ????
• ?????? CAD ?????????...

18
??????

• ??????????, ????????????
• ???? Full-time RA or special mission
• ??????????
• ???, notebook, printers, paper DB, EDA tools,
  etc.
• ?????????, ?????.
• ???? ???? ????
• ??, team building events, ??, etc.
• ? Google Calendar ?? meeting ??

19
For more information...http//dvlab.ee.ntu.edu.tw

20
For more information...PTT ? NTUGIEE_ric
21
For more information...Lab DB (password required)
22
For more information...

• To find me
• Office EE-II 444
• ric_at_cc.ee.ntu.edu.tw
• ric2k1 _at_ ptt, ptt2, msn, skype, ...
• 02-3366-3644
• Lab
• EE-II 353
• PTT NTUGIEE_ric
• Website http//dvlab.ee.ntu.edu.tw/