Transistor and Circuit Design for 100-200 GHz ICs

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Transistor and Circuit Design for 100-200 GHz
ICs
2004 IEEE Compound Semiconductor IC Symposium,
October, Monterey
Mark Rodwell University of California, Santa
Barbara
V. Paidi, Z. Griffith, D. Scott, Y. Dong, M.
Dahlström, Y. Wei, N. ParthasarathyUniversity of
California, Santa Barbara Lorene Samoska, Andy
FungJet Propulsion Laboratories M. Urteaga, R.
Pierson , P. Rowell, B. BrarRockwell Scientific
Company S. Lee, N. Nguyen, and C. NguyenGlobal
Communication Semiconductors
rodwell_at_ece.ucsb.edu 805-893-3244, 805-893-5705
fax
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Potential applications for 100-300 GHz Electronics
Optical Fiber Transmission 40 Gb/s InP and SiGe
ICs commercially available 80 160 Gb/s is
feasible 80-160 Gb/s InP ICs now clearly feasible
100 GHz modulators demonstrated (KTH
Stockholm)100 GHz photodiodes demonstrated in
1980'schallenge limit to range due to fiber
dispersionchallenge competition with WDM using
10 Gb CMOS ICs
40 Gb/s InP HBT fiber chip set (Gtran Inc.)
100 Gb/s over 1 km in heavy rain 250 GHz carrier
Radio-wave Transmission / Radar / Imaging 65-80
GHz, 120-160 GHz, 220-300 GHz100 Gb/s
transmission over 1 km in heavy rain300 GHz
imaging for foul-weather aviation sciencespectros
copy, radio astronomy
300 GHz imagining radar for foul-weather aviation
Mixed-Signal ICs for Military Radar/Comms
direct digital frequency synthesis, ADCs,
DACshigh resolution at very high bandwidths
sought
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Fast IC Technologies
SiGe HBT Advantages superior scaling
extrinsic parasitic reduction CMOS
integration Performance 130 nm scaling
generation 210 GHz ft / 270GHz fmax 96 GHz
static dividers 77 GHz amplifiers 150 GHz
push-push VCO- 75 GHz fundamental
SOI CMOS Advantages cost, power, integration
scales Performance 90 nm scaling
generation 200 GHz ft fmax 60 GHz 21
mux 91 GHz amplifiers
InP HBT Advantages 3.5x107 cm/s collector
velocity 500 Ohm/square base sheet
r Performance 500 nm scaling generation 400
GHz ft / 500 GHz fmax 4 V breakdown 150 GHz
static dividers 178 GHz amplifiers Comments
scaling will improve bandwidth scaling can
reduce power small market lt-gt high cost
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Optical Transmitters / Receivers are Mixed-Signal
ICs
MUX/CMU DMUX/CDR mostly digital
TIA small-signal
LIA often limiting
Small-signal cutoff frequencies (ft , fmax) are
predictive of analog speedLimiting and digital
speed much more strongly determined by I/C ratios
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We design HBTs for low gate delay, not for high
ft fmax
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Why isn't basecollector transit time so
important for logic?
Depletion capacitances present over full voltage
swing, no large-signal reduction
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Scaling Laws, Collector Current Density, Ccb
charging time
InGaAs base
GaAsSb base
Collector Depletion Layer Collapse
Collector Field Collapse (Kirk Effect)
Collector capacitance charging time scales
linearly with collector thickness if J Jmax
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Key HBT Scaling Limit ? Emitter Resistance
ECL delay not well correlated with f? or fmax
Largest delay is charging Ccb
? Je ? 10 mA/?m2 needed for 200 GHz clock rate
Voltage drop of emitter resistance becomes
excessive RexIc ?exJe (15 ???m2) ? (10
mA/?m2) 150 mV ? considerable fraction of
?Vlogic ? 300 mV Degrades logic noise margin
? ?ex ? 7 ???m2 needed for 200 GHz clock rate
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Breakdown Thermal failure is more significant
than BVCEO
Low thermal resistance is critical. DHBTs are
superior to SHBTs.
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Bipolar Transistor Scaling Laws Scaling Roadmaps
Scaling Lawsdesign changes required to double
transistor bandwidth
InP Technology Roadmap 40 / 80 / 160 Gb/s
digital clock rate
key device parameter required change
collector depletion layer thickness decrease 21
base thickness decrease 1.4141
emitter junction width decrease 41
collector junction width decrease 41
emitter resistance per unit emitter area decrease 41
current density increase 41
base contact resistivity (if contacts lie above collector junction) decrease 41
base contact resistivity (if contacts do not lie above collector junction) unchanged
key figures of merit for logic speed
Key scaling challengesemitter base contact
resistivitycurrent density? device
heatingcollector-base junction width scaling
Yeild !
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InP DHBTs 600 nm emitter width, 150 nm thick
collector
Zach Griffith
391 GHz f? , 505 GHz fmax
Ccb/Ic 0.5 ps/V
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CPW has parasitic modes, coupling from poor
ground plane integrity
V
0V
V
V
V
0V
0V
0V
Substrate modes
CPW mode
Microstrip mode
ground straps suppress slot mode, but multiple
ground breaks in complex ICs produce ground
return inductance ground vias suppress microstrip
mode, wafer thinning suppresses substrate modes
Microstrip has high via inductance, has mode
coupling unless substrate is thin.
kz
We prefer (credit to NTT) thin-film microstrip
wiring, inverted is best for complex ICs
M. Urteaga, Z. Griffith, S. Krishnan
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IC design Zach Griffith, UCSBHBT design RSC /
UCSB / GCSIC Process / Fabrication GCSTest
UCSB / RSC / Mayo
UCSB / RSC / GCS 150 GHz Static Frequency Dividers
units data current steering data emitter followers clock current steering clock emitter followers
size mm2 0.5 x 3.5 0.5 x 4.5 0.5 x 4.5 0.5 x 5.5
currentdensity mA/mm2 6.9 4.4 4.4 4.4
Ccb/Ic psec / V 0.59 0.99 0.74 0.86
Vcb V 0.6 0 0.6 1.7
ft GHz 301 260 301 280
fmax GHz 358 268 358 280
PDC,total 659.8 mW divider core without output
buffer ? 594.7 mW
probe station chuck _at_ 25?C
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Z. Griffith, M. Dahlström
UCSB 142 GHz Master-Slave Latches (Static
Frequency Dividers)
Static 21 dividerStandard digital
benchmark.Master-slave latch with inverting
feedback.Performance comparison between digital
technologies UCSB technology 2004InP mesa HBT
technology12-mask process600 nm emitter
width142 GHz maximum clock. Implications 160
Gb/s fiber ICs 100 Gb/s serial links Target is
260 GHz clock rate at 300 nm scaling generation
25o C
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Reducing Divide-by-2 Dissipation
50 Ohm bus
50 Ohm
50 Ohm
ECL with impedance-matched 50 Ohm bus25 Ohm
load? switch 12 mA 12 mA x 7 x 4 V 336
mW/latch
12 mA
50 Ohm bus
50 Ohm
50 Ohm
CML with impedance-matched 50 Ohm bus25 Ohm
load? switch 12 mA 12 mA x 3 x 3 V 108
mW/latch
12 mA
12 mA
12 mA
50 Ohm bus
100 Ohm
Low-Power CML100 Ohm loaded ? switch 3 mA 3 mA
x 3 x 3 V 27 mW/latch
3 mA
What parts of circuit are included in stated
dissipation ?
3 mA
3 mA
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Mesa DHBT Power Amplifiers for 100-200 GHz
Communications
V. Paidi, Z. Griffith, M. Dahlström
7 dB gain measured _at_ 175 GHz
7.5 mW output power
175 GHz Power Amplifier Demonstrated in a 300 GHz
fmax process500 GHz fmax DHBTs available now,
600 GHz should be feasible soon ? feasibility
of power amplifiers to 350 GHz ? Ultra high
frequency communications
2 fingers x 0.8 um x 12 um, 250 GHz ft, 300 GHz
fmax , Vbr 7V, 3 mA/um2 current density
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172 GHz Common-Base Power Amplifier
V. Paidi, Z. Griffith, M. Dahlström
8.3 dBm saturated output power 4.5-dB associated
power gain at 172 GHz DC bias Ic47 mA,
Vcb2.1V.
6 dB gain
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176 GHz Two-Stage Amplifier
V. Paidi, Z. Griffith, M. Dahlström
7-dB gain at 176 GHz 8.1 dBm output power, 6.3 dB
power gain at 176 GHz 9.1 dBm saturated output
power at 176 GHz
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InP HBT limits to yield non-planar process
Griffith, Dahlström
Yield quickly degrades as emitters are scaled to
submicron dimensions
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Parasitic Reduction for Improved InP HBT Bandwidth
At a given scaling generation, intelligent choice
of device geometry reduces extrinsic parasitics
wide emitter contact low resistance narrow
emitter junction scaling (low Rbb/Ae)
thick extrinsic base low resistance thin
intrinsic base low transit time
wide base contacts low resistancenarrow
collector junction low capacitance
These are planar approximations toradial
contacts
extrinsic emitter
extrinsic base
extrinsic base
N subcollector
? greatly reduced access resistance
Much more fully developed in Si
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UCSB/RSC/GCS TFAST HBT Technology Development
Scaled mesa-HBT
S3 Technology
Regrowth Technology

• High performance, low yield technology
• Difficult to scale to WE lt 0.4 um
• Processed for epitaxy and circuit validation

• Improved base-emitter process flow
• Process scalable to WE lt 0.25 um

• Process modules that can be added to HBT
  technology
• Emitter regrowth for high yield, low Re
• Extrinsic base for low Rbb
• Pedestal implant for reduced Ccb
• Allows continued scaling even if base emitter
  contact resistivities do not improve.

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Low Parasitic, Scalable HBT processes
Collector pedestal implant
Extrinsic emitter regrowth
Emitter sidewall process
Miguel Urteaga
Independent control of base contact collector
junction widths ? reduced capacitance
SiGe-like emitter-base process wide emitter
contact ? low resistancethick extrinsic base ?
low resistance
high-yield (10,000 transistor)alternative to
emitter-base definition by mesa etch
Yingda Dong
Dennis Scott, Yun Wei
RSC/GCS/UCSBVitesse similar to earlier Hitachi,
NEC, NTT GaAs HBT processes
RSC/GCS/UCSBNorthrup Grumman
RSC/GCS/UCSBHRL Labs
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Collector Pedestal Implant for InP HBTs
Y. Dong et. al. ISDRC December 2003, DRC June
2004

• large collector capacitance reductionsignificant
  increase in breakdown2(1013) V-sec Johnson
  Figure-of-Merit transistors have low leakage,
  good DC characteristics

Pedestal can be integrated into sidewall or
mesa emitter processes, emitter regrowth process
Good DC characteristics, high power
density,increased breakdown 5.4 V with a 90
nm thick collector
21 reduction in collector base capacitance
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What's next ? 250 nm Scaling Generation for gt200
GHz clock
sidewall processes for 300 nm at high yield
narrow collector junctions needed low
contact resistivity modified sidewall spacer
process /or collector pedestal
power density near reliability limits narrow
emitters should improve heatsinking
Decreasing Acollector/Aemitter decreases required
Je eases thermal design
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Indium Phosphide HBTs for 100-200 GHz ICs
InP HBT high speed room left to scale
150 GHz digital clock (static divider) at 500 nm
scaling generation 210 GHz clock should
soon be feasible at 250 nm scaling. low
NRE low mask cost Applications feasible soon
160 Gb fiber ICs, 300 GHz MIMICs for
communications radar GHz mixed-signal ICs
for radar communications Planar processes
address yield limitations emitter-base
junction liftoff-free dielectric sidewall
process base-collector junction planar
implanted process Volume markets are needed to
drive down cost GaAs HBT power amplifier
processes are cheap Why can't InP HBT be
inexpensive ? InP HBT can be scaled at
high yieldKey to survival of the technology are
emergence of singificant markets progress
relative to CMOS InP