William Stallings Computer Organization and Architecture 7th Edition

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William Stallings Computer Organization and
Architecture7th Edition

• Chapter 5
• Internal Memory

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Semiconductor Memory Types
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Semiconductor Memory

• RAM
• Misnamed as all semiconductor memory is random
  access
• Read/Write
• Volatile
• Temporary storage
• Static or dynamic

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Memory Cell Operation
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Dynamic RAM

• Bits stored as charge in capacitors
• Charges leak
• Need refreshing even when powered
• Simpler construction
• Smaller per bit
• Less expensive
• Need refresh circuits
• Slower
• Main memory
• Essentially analogue
• Level of charge determines value

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Dynamic RAM Structure
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DRAM Operation

• Address line active when bit read or written
• Transistor switch closed (current flows)
• Write
• Voltage to bit line
• High for 1 low for 0
• Then signal address line
• Transfers charge to capacitor
• Read
• Address line selected
• transistor turns on
• Charge from capacitor fed via bit line to sense
  amplifier
• Compares with reference value to determine 0 or 1
• Capacitor charge must be restored

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Static RAM

• Bits stored as on/off switches
• No charges to leak
• No refreshing needed when powered
• More complex construction
• Larger per bit
• More expensive
• Does not need refresh circuits
• Faster
• Cache
• Digital
• Uses flip-flops

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SRAM v DRAM

• Both volatile
• Power needed to preserve data
• Dynamic cell
• Simpler to build, smaller
• More dense
• Less expensive
• Needs refresh
• Larger memory units
• Static
• Faster
• Cache

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Read Only Memory (ROM)

• Permanent storage
• Nonvolatile
• Microprogramming (see later)
• Library subroutines
• Systems programs (BIOS)
• Function tables

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Types of ROM

• Written during manufacture
• Very expensive for small runs
• Programmable (once)
• PROM
• Needs special equipment to program
• Read mostly
• Erasable Programmable (EPROM)
• Erased by UV
• Electrically Erasable (EEPROM)
• Takes much longer to write than read
• Flash memory
• Erase whole memory electrically

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Organisation in detail

• A 16Mbit chip can be organised as 1M of 16 bit
  words
• A bit per chip system has 16 lots of 1Mbit chip
  with bit 1 of each word in chip 1 and so on
• A 16Mbit chip can be organised as a 2048 x 2048 x
  4bit array
• Reduces number of address pins
• Multiplex row address and column address
• 11 pins to address (2112048)
• Adding one more pin doubles range of values so x4
  capacity

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William Stallings Computer Organization and
Architecture7th Edition

• Chapter 4
• Cache Memory

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Location

• CPU
• Internal
• External

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Locality of Reference

• During the course of the execution of a program,
  memory references tend to cluster
• e.g. loops

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Cache

• Small amount of fast memory
• Sits between normal main memory and CPU
• May be located on CPU chip or module

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Cache/Main Memory Structure
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Cache operation overview

• CPU requests contents of memory location
• Check cache for this data
• If present, get from cache (fast)
• If not present, read required block from main
  memory to cache
• Then deliver from cache to CPU
• Cache includes tags to identify which block of
  main memory is in each cache slot

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Cache Read Operation - Flowchart
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Typical Cache Organization
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Performace of Cache Systems

• Let
• tc cache access time
• h hit ratio
• tm memory access time
• Average access time ( AT ) htc(1-h)(tc
  tm )
• Ration of memory access time to cache access time
  (g ) tm / tc
• Efficiency tc / AT
• Example
• Let tc 160 ns, tm 960ns, h0.90
• Calculate Effceincy, AT, and g
• AT0.9160 (1-0.9)(960160)
• 144112256 ns
• g 960/1606
• Efficiency 160/2560.625

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Direct Mapping

• Each block of main memory maps to only one cache
  line
• i.e. if a block is in cache, it must be in one
  specific place
• Address is in two parts
• Least Significant w bits identify unique word
• Most Significant s bits specify one memory block
• The MSBs are split into a cache line field r and
  a tag of s-r (most significant)

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Cache Memory Techniques

• Fully Associative Mapping
• Direct Mapping
• Set Associative Mapping

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Fully Associative Mapping

• In fully Associative Mapping, a main memory block
  i can be mapped to any cache block j.

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• To determine which block of main memory is stored
  into cache, a tag is required for each cache
  block
• Tag(j) address of memory block stored in cache
  block j
• ?Assume that M2m then the tag should at least
  store the m bits
• When CPU generates an address, the main memory
  block is extracted and then associatively
  compared with the tags for a match. If a match
  occurs, the corresponding cache block number is
  retrieved and the cache is accessed for the
  required data

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Direct Mapping

• To reduce the cost of the associated memory,
  direct mapping is used. The memory block i is
  always mapped into cache I mode N.

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Associative set

• Instead of directly map the memory block into a
  certain block in the cache, the memory block can
  be mapped in a set of cache blocks. These blocks
  can be then associatively mapped.