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Finite State Machine Basics

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Title: VHDL Structural Modeling II Last modified by: Ron Hayne Created Date: 10/19/1997 12:54:42 PM Document presentation format: On-screen Show Other titles – PowerPoint PPT presentation

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Title: Finite State Machine Basics


1
Finite State Machine Basics
  • ECE-331, Digital Design
  • Dr. Ron Hayne
  • Electrical and Computer Engineering

2
Automata vs Combinational
  • Combinational Circuits
  • No feedback
  • Boolean Algebraic mapping of input binary values
    to output value(s)
  • Finite State Machines
  • Feedback
  • State and input dependent output

3
Automata Model
4
Finite State Machine
  • Combinational Circuit Generates
  • Excitation variables for synchronous FSMs, or
  • Next state variables for asynchronous FSMs
  • Memory
  • Feedback from output to input
  • Can be as simple as time delay for asynch FSM
  • Usually flip-flops for synch FSM

5
Abstract Model of FSM
  • Machine is a quintuple of sets
  • M ( S, I, O, ?, ? )
  • S Finite set of states
  • I Finite set of inputs
  • O Finite set of outputs
  • ? State transition function
  • ?/? Mealy/Moore output function

6
FSM and Clocks
  • Synchronous FSMs may change state only when a
    unique input, the clock, occurs
  • Asynchronous FSMs may change state when input
    changes
  • Next state depends on present input and present
    state for both Moore and Mealy

7
Synchronous Moore Machine
Input
Comb Ckt
Output
Present State
Next State
Output Is Only a Function of Present State
Clock
8
Synchronous Mealy Machine
Input
Comb Ckt
Output
Present State
Next State
Output Is Function of Present State AND Present
Input
Clock
9
Primitive State Diagram, Moore
10
Moore Machine State Diagram
11
Primitive State Diagram, Mealy
12
Mealy Machine State Diagram
13
Unsolved FSM Design Problem
  • Mapping of Primitive States to Binary Numeric
    Representation Is Not Unique
  • Some Mappings Are Better Than Others Since They
    Can Be Implemented in Less Hardware and Operate
    Faster
  • Usual Solution Is to Make Large FSM Out of
    Smaller FSMs and Try All Mappings for Smaller
    Machines (ECE-548)

14
It can be shown that ...
  • Any Mealy Machine Can Be Converted to a
    Behaviorally Equivalent Moore Machine and
    Vice-Versa
  • An Incompletely Specified Machine Can Be
    Converted to a Completely Specified Machine
    Through the Addition of States

15
FSM Design Approaches
  • One-Hot
  • One flip-flop is used to represent each state
  • Costly in terms of hardware, but trivial to
    design
  • Binary Coded State
  • n flip-flops used to store 2n states
  • Most efficient
  • Need to account for unused states

16
Mealy Machine, e.g.
  • Rabin-Scott Machine
  • Language Recognizer
  • Detect the sequence 0101
  • String input left to right
  • Continues to function if longer string
  • detects last four characters
  • non-resetting

17
Mealy 0101 Detector
  • M ( S, I, O, ?, ? )
  • S A, B, C, D
  • I 0, 1
  • O 0, 1 not detected, detected
  • ? next slides
  • ? next slides

18
0101 State Diagram
0 detected
A
B
19
0101 State Diagram
0/0
0 detected
1/0
A
B
0/0
1/0
C
01 det
20
0101 State Diagram
0/0
0 detected
1/0
A
B
0/0
1/0
1/0
D
C
0/0
01 det
010 det
21
0101 State Diagram
0/0
0 detected
1/0
A
B
0/0
1/0
0/0
1/0
1/1
D
C
0/0
01 det
010 det
22
Mealy Transition/Output Table
Next State/Output
23
Moore 0101 Detector
  • M ( S, I, O, ?, ? )
  • S A, B, C, D, E
  • I 0, 1
  • O 0, 1 not detected, detected
  • ? next slide
  • ? next slide

24
Moore Transition/Output Table
Next State
25
Moore 0101 State Diagram
0
1
0 detected
0
A/0
B/0
0
1
1
1
0101 det
C/0
0
0
01 det
1
010 det
26
Moore/Mealy
  • More States in Moore Than in Behavioral
    Equivalent Mealy
  • Mealy
  • Usually pulse output (during transition)
  • Moore
  • Usually level output (during state)

27
Summary
  • FSM
  • Synchronous
  • Asynchronous
  • Moore
  • Mealy
  • Example
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