Computer-Aided Design Concept to Silicon

1
Computer-Aided DesignConcept to Silicon

• Victor P. Nelson

2
ASIC Design Flow
Behavioral Model VHDL/Verilog
Verify Function
Synthesis
DFT/BIST ATPG
Gate-Level Netlist
Verify Function
Full-custom IC
Test vectors
Transistor-Level Netlist
Verify Function Timing
Standard Cell IC FPGA/CPLD
Physical Layout Map/Place/Route
Verify Timing
DRC LVS Verification
IC Mask Data/FPGA Configuration File
3
Mentor Graphics CAD Tools (select from eda
list in user-setup on the Sun network)

• ICFlow2007.2 For custom standard cell IC
  designs
• IC flow tools (Design Architect-IC, IC Station,
  Calibre)
• Digital/analog/mixed simulation (Modelsim,ADVance
  MS,Eldo,MachTA)
• HDL Synthesis (Leonardo)
• DFT/2006.3
• ATPG/DFT/BIST tools (DFT Advisor, Flextest,
  Fastscan)
• Modelsim/6.3c (HDL Simulation)
• FPGA/2004 (FPGA Advantage, Modelsim, Leonardo)
• Xilinx/ISE8.2i (Xilinx FPGA/CPLD - back end
  design)
• QuartusII/5.0 (Altera FPGA/CPLD - back end
  design)
• Ims/6.2 (IMS chip tester)
• Vendor-Provided (Not Mentor Graphics)
  Tools

4
Mentor Graphics ASIC Design Kit (ADK)

• Technology files standard cell libraries
• AMI ami12, ami05 (1.2, 0.5 µm)
• TSMC tsmc035, tsmc025, tsmc018 (0.35, 0.25, 0.18
  µm)
• IC flow DFT tool support files
• Simulation
• VHDL/Verilog/Mixed-Signal models
  (Modelsim/ADVance MS)
• Analog (SPICE) models (Eldo/Accusim)
• Post-layout timing (Mach TA)
• Digital schematic (Quicksim II, Quicksim Pro)
  (exc. tsmc025,tsmc018)
• Synthesis to std. cells (LeonardoSpectrum)
• Design for test ATPG (DFT Advisor,
  Flextest/Fastscan)
• Schematic capture (Design Architect-IC)
• IC physical design (standard cell custom)
• Floorplan, place route (IC Station)
• Design rule check, layout vs schematic, parameter
  extraction (Calibre)

5
Xilinx/Altera FPGA/CPLD Design

• Simulate designs in Modelsim
• Behavioral models (VHDL,Verilog)
• Synthesized netlists (VHDL, Verilog)
• Requires primitives library for the target
  technology
• Synthesize netlist from behavioral model
• Leonardo has libraries for most FPGAs
• Xilinx ISE has its own synthesis tool
• Vendor tools for back-end design
• Map, place, route, configure device, timing
  analysis, generate timing models
• Xilinx Integrated Software Environment (ISE)
• Altera Quartus II MaxPlus2
• Higher level tools for system design management
• Mentor Graphics FPGA Advantage
• Xilinx Platform Studio SoC design, IP
  management, HW/SW codesign

6
Behavioral Design Verification(mostly
technology-independent)
Create Behavioral/RTL HDL Model(s)
VHDL Verilog SystemC
VHDL-AMS Verilog-A
Simulate to Verify Functionality
ModelSim (digital)
ADVance MS (analog/mixed signal)
Leonardo Spectrum, Xilinx ISE (digital)
Synthesize Circuit
Technology Libraries
Post-Layout Simulation, Technology-Specific
Netlist to Back-End Tools
7
ADVance MS Simulation System

• ADVance MS kernel supports
• VHDL Verilog digital (via ModelSim)
• VHDL-AMS Verilog-A analog/mixed signal
• Eldo/SPICE analog (via Eldo)
• Eldo RF/SPICE analog RF (via Eldo RF)
• Mach TA/SPICE high-speed analog/timing
• Invoke stand-alone or from Design Architect-IC

8
ADVance MSDigital, Analog, Mixed-Signal
Simulation
VHDL,Verilog, VHDL-AMS, Verilog-A, SPICE Netlists
VITAL
SPICE models
Xilinx simprims
Design_1 Design_2
IEEE 1164
Working Library
Resource Libraries
ADVance MS
Input Stimuli
Simulation Setup
Mixed Signal (VHDL-AMS, Verilog-A)
EZwave or Xelga
Eldo, Eldo RF
ModelSim
View Results
Mach TA Mach PA
Analog (SPICE)
Digital (VHDL,Verilog)
9
Example 4-bit binary counter

• VHDL model (count4.vhd)
• Create working library vlib work
• vmap work
  work
• Compile vcom count4.vhd
• Simulate vsim count4(rtl)
• ModelSim simulation-control inputs
• ModelSim Macro (count4_rtl.do)
• OR, VHDL testbench
• ModelSim results
• listing or waveform

10

• -- count4.vhd 4-bit parallel-load synchronous
  counter
• LIBRARY ieee
• USE ieee.std_logic_1164.all USE
  ieee.numeric_std.all --synthesis libraries
• ENTITY count4 IS
• PORT (clock,clear,enable,load_count IN
  STD_LOGIC
• D IN unsigned(3 downto 0)
• Q OUT unsigned(3 downto 0))
• END count4
• ARCHITECTURE rtl OF count4 IS
• SIGNAL int unsigned(3 downto 0)
• BEGIN
• PROCESS(clear, clock, enable)
• BEGIN
• IF (clear '1') THEN
• int lt "0000"
• ELSIF (clock'EVENT AND clock'1') THEN
• IF (enable '1') THEN

11
Test stimulusModelsim do file count4_rtl.do

• add wave /clock /clear /enable /load_count /D /Q
• add list /clock /clear /enable /load_count /D /Q
• force /clock 0 0, 1 10 -repeat 20
• force /clear 0 0, 1 5, 0 10
• force /enable 0 0, 1 25
• force /load_count 0 0, 1 20, 0 35, 1 330, 0 350
• force /D 105 0, 109 300
• run 400

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Testbench count4_bench.vhd

• LIBRARY ieee USE ieee.std_logic_1164.all USE
  ieee.numeric_std.all
• ENTITY count4_bench is end count4_bench
• ARCHITECTURE test of count4_bench is
• component count4
• PORT (clock,clear,enable,load_count IN
  STD_LOGIC
• D IN unsigned(3 downto 0)
• Q OUT unsigned(3 downto 0))
• end component
• for all count4 use entity work.count4(behavior
  )
• signal clk STD_LOGIC '0'
• signal clr, en, ld STD_LOGIC
• signal din, qout unsigned(3 downto 0)
• begin
• UUT count4 port map(clk,clr,en,ld,din,qout)
• clk lt not clk after 10 ns
• P1 process
• begin
• din lt "0101" clr lt '1' en lt '1'
  ld lt '1'

Alternative to do file
Could also check results assert error messages
13
Count4 Simulation waveform
Clear
Counting
Parallel Load
14
ADVance MS mixed-signal simulation
A/D converter
digital analog VHDL-AMS
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ADVance MS mixed Verilog-SPICE
Verilog top (test bench)
SPICE subcircuit
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Automated Synthesis with Leonardo Spectrum
VHDL/Verilog Behavioral/RTL Models
Technology Synthesis Libraries
Leonardo Spectrum (Level 3)
FPGA
Design Constraints
ASIC
ADK AMI 0.5, 1.2 TSMC 0.35, 0.25
Level 1 FPGA Level 2 FPGA Timing Level 3
ASIC FPGA
Technology- Specific Netlist
VHDL, Verilog, SDF, EDIF, XNF
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Leonardo ASIC Synthesis Flow
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Leonardo synthesis procedure

• Invoke leonardo
• Select load a technology library (ASIC or FPGA)
• ASIC gt ADK gt TSMC 0.35 micron
• Read input VHDL/Verilog file(s) count4.vhd
• Enter any constraints (clock freq, delays, etc.)
• Optimize for area/delay/effort level
• Write output file(s)
• count4_0.vhd - VHDL netlist
• count4.v - Verilog netlist (for IC
  layout)
• count4.sdf - Standard delay format file
  (for timing)
• count4.edf - EDIF netlist (for
  Xilinx/Altera FPGA)

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• Leonardo-synthesized netlist count4_0.vhd
• library IEEE use IEEE.STD_LOGIC_1164.all
• library adk use adk.adk_components.all --
  ADDED BY VPN
• entity count4 is
• port (
• clock IN std_logic clear IN
  std_logic enable IN std_logic load_count
  IN std_logic
• D IN std_logic_vector (3 DOWNTO 0) Q
  OUT std_logic_vector (3 DOWNTO 0))
• end count4
• architecture netlist of count4 is -- rtl
  changed to netlist by VPN
• signal Q_3_EXMPLR, Q_2_EXMPLR, Q_1_EXMPLR,
  Q_0_EXMPLR, nx8, nx14, nx22,
• nx28, nx48, nx54, nx62, nx126, nx136,
  nx146, nx156, nx169, nx181,
• nx183, nx185, nx187, nx189 std_logic
  
• begin
• Q(3) lt Q_3_EXMPLR Q(2) lt Q_2_EXMPLR
  Q(1) lt Q_1_EXMPLR Q(0) lt Q_0_EXMPLR
• Q_0_EXMPLR_EXMPLR dffr port map (
  QgtQ_0_EXMPLR, QBgtOPEN, Dgtnx126, CLKgtclock,
  Rgtclear)
• ix127 mux21_ni port map ( Ygtnx126,
  A0gtQ_0_EXMPLR, A1gtnx8, S0gtenable )
• ix9 oai21 port map ( Ygtnx8,
  A0gtload_count, A1gtQ_0_EXMPLR, B0gtnx169 )
• ix170 nand02 port map ( Ygtnx169, A0gtD(0),
  A1gtload_count)

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• // Verilog description for cell count4,
  LeonardoSpectrum Level 3, 2005a.82
• module count4 ( clock, clear, enable, load_count,
  D, Q )
• input clock
• input clear
• input enable
• input load_count
• input 30D
• output 30Q
• wire nx8, nx14, nx22, nx28, nx48, nx54, nx62,
  nx126, nx136, nx146, nx156, nx169, nx181, nx183,
  nx185, nx187, nx189
• wire 30 \dummy
• dffr Q_0__rename_rename (.Q (Q0), .QB
  (\dummy 0), .D (nx126), .CLK (clock), .R
  (clear))
• mux21_ni ix127 (.Y (nx126), .A0 (Q0), .A1
  (nx8), .S0 (enable))
• oai21 ix9 (.Y (nx8), .A0 (load_count), .A1
  (Q0), .B0 (nx169))
• nand02 ix170 (.Y (nx169), .A0 (D0), .A1
  (load_count))
• dffr Q_1__rename_rename (.Q (Q1), .QB
  (\dummy 1), .D (nx136), .CLK (clock), .R
  (clear))
• mux21_ni ix137 (.Y (nx136), .A0 (Q1), .A1
  (nx28), .S0 (enable))
• ao22 ix29 (.Y (nx28), .A0 (D1), .A1
  (load_count), .B0 (nx14), .B1 (nx22) )

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Post-synthesis simulation(Leonardo-generated
netlist)

• Verify synthesized netlist matches behavioral
  model
• Create simulation primitives library for std
  cells
• gtvlib adk
• gtvcom ADK/technology/adk.vhd
• gtvcom ADK/technology/adk_comp.vhd
• Insert library/package declaration into netlist
• library adk
• use adk.adk_components.all
• Simulate in Modelsim, using do file or test
  bench from original behavioral simulation
• results should match

VITAL models of all ADK std cells
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Post-synthesis timing analysis

• Leonardo can generate SDF (std. delay format)
  file with technology-specific, VITAL-compliant
  timing parameters.
• (CELLTYPE "dffr")
• (INSTANCE Q_0_EXMPLR_EXMPLR)
• (DELAY
• (ABSOLUTE
• (PORT D (0.00) (0.00))
• (PORT CLK (0.00) (0.00))
• (PORT R (0.00) (0.00))
• (IOPATH CLK Q (0.40) (0.47))
• (IOPATH R Q (0.00) (0.55))
• (IOPATH CLK QB (0.45) (0.36))
• (IOPATH R QB (0.53) (0.00))))
• (TIMINGCHECK
• (SETUP D (posedge CLK) (0.47))
• (HOLD D (posedge CLK) (-0.06))))

Delays lumped at pins
Path delays (mintypmax)
Constraints
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VITAL Model (1)

• library IEEE use IEEE.STD_LOGIC_1164.all
• use IEEE.VITAL_Primitives.all use
  IEEE.VITAL_Timing.all
• entity and02 is
• generic (
• tipd_A0 VitalDelayType01Z
  VitalZeroDelay01Z
• tipd_A1 VitalDelayType01Z
  VitalZeroDelay01Z
• tpd_A0_Y VitalDelayType01Z
  VitalZeroDelay01Z
• tpd_A1_Y VitalDelayType01Z
  VitalZeroDelay01Z
• )
• port (
• A0 in STD_LOGIC
• A1 in STD_LOGIC
• Y out STD_LOGIC
• )
• attribute VITAL_LEVEL0 of and02 entity is
  TRUE
• end and02

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VITAL Model (2)

• architecture and02_arch of and02 is
• attribute VITAL_LEVEL1 of and02_arch
  architecture is TRUE
• signal A0_ipd STD_LOGIC 'X'
• signal A1_ipd STD_LOGIC 'X'
• begin
• WireDelay Block
• begin
• VitalWireDelay (A0_ipd, A0, tipd_A0)
• VitalWireDelay (A1_ipd, A1, tipd_A1)
• end Block
• VitalBehavior Process (A0_ipd, A1_ipd)
• VARIABLE INT_RES_0 STD_LOGIC 'X'
• VARIABLE GlitchData_Y VitalGlitchDataType
• begin
• -- FUNCTIONALITY SECTION --
• INT_RES_0 VitalAnd2 (A0_ipd, A1_ipd)

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VITAL Model (3)

• -- PATH DELAY SECTION --
• VitalPathDelay01Z (
• OutSignal gt Y,
• OutSignalName gt "Y",
• OutTemp gt INT_RES_0,
• Paths gt (
• 0 gt ( InputChangeTime gt A0_ipd'LAST_EVENT,
• PathDelay gt tpd_A0_Y,
• PathCondition gt TRUE
• ),
• 1 gt ( InputChangeTime gt A1_ipd'LAST_EVENT,
• PathDelay gt tpd_A1_Y,
• PathCondition gt TRUE
• )
• ),
• GlitchData gt GlitchData_Y,
• Mode gt OnDetect,
• MsgOn gt TRUE, Xon gt TRUE,
• MsgSeverity gt WARNING

26
Design for test test generation

• Consider test during the design phase
• Test design more difficult after design frozen
• Basic steps
• Design for test (DFT) insert test points, scan
  chains, etc. to improve testability
• Insert built-in self-test (BIST) circuits
• Generate test patterns (ATPG)
• Determine fault coverage (Fault Simulation)

27
DFT test design flow
Memory Logic BIST
Boundary Scan
Internal Scan Design
ATPG
28
DFTadvisor/FastScan Design Flow
count4.vhd
count4_0.vhd count4.v
DFT/ATPG Library adk.atpg
count4_scan.v
Source FlexTest Manual
29
ASIC DFT Flow
Synthesized VHDL/Verilog Netlist
ATPG Library
Insert Internal Scan Circuitry
DFT Advisor
adk.atpg
VHDL/Verilog Netlist With Scan Elements
Generate/Verify Test Vectors
Fastscan/ Flextest
Test Pattern File
30
Example DFTadvisor session

• Invoke
• dftadvisor verilog count4.v lib
  ADK/technology/adk.atpg
• Implement scan with defaults
• (full scan, mux-DFF scan elements)
• set system mode setup
• analyze control signals auto
• set system mode dft
• run
• insert test logic
• write netlist count4_scan.v verilog
• write atpg setup count4_scan
• (creates count4_scan.dofile for ATPG in
  Fastscan)

31
count4 without scan design
32
count4 scan inserted by DFTadvisor
33
ATPG with FastScan (full-scan circuit)

• Invoke
• fastscan verilog count4.v lib
  ADK/technology/adk.atpg
• Generate test pattern file in FastScan
• dofile count4_scan.dofile (defines scan path
  procedure)
• set system mode atpg
• create patterns auto (generate test
  patterns)
• save patterns

Note count4_scan.dofile created by DFTadvisor
34
Test file scan chain definition and load/unload
procedures

• scan_group "grp1"
• scan_chain "chain1"
• scan_in "/scan_in1"
• scan_out "/output3"
• length 4
• end
• procedure shift "grp1_load_shift"
• force_sci "chain1" 0
• force "/clock" 1 20
• force "/clock" 0 30
• period 40
• end
• procedure shift "grp1_unload_shift"
• measure_sco "chain1" 10
• force "/clock" 1 20
• force "/clock" 0 30
• period 40
• end

• procedure load "grp1_load"
• force "/clear" 0 0
• force "/clock" 0 0
• force "/scan_en" 1 0
• apply "grp1_load_shift" 4 40
• end
• procedure unload "grp1_unload"
• force "/clear" 0 0
• force "/clock" 0 0
• force "/scan_en" 1 0
• apply "grp1_unload_shift" 4 40
• end
• end

35
Generated scan-based test

• // send a pattern through the scan chain
• CHAIN_TEST
• pattern 0
• apply "grp1_load" 0 (use
  grp1_load procedure)
• chain "chain1" "0011" (pattern to
  scan in)
• end
• apply "grp1_unload" 1 (use
  grp1_unload procedure)
• chain "chain1" "1100" (pattern
  scanned out)
• end
• end
• // one of 14 patterns for the counter circuit
• pattern 0 (pattern
  )
• apply "grp1_load" 0 (load scan
  chain)
• chain "chain1" "1000" (scan-in
  pattern)
• end
• force "PI" "00110" 1 (PI pattern)
• measure "PO" "0010" 2 (expected POs)
• pulse "/clock" 3 (normal
  op. cycle)
• apply "grp1_unload" 4 (read scan
  chain)

36
ASIC Physical Design (Standard Cell)(can also
do full custom layout)
Component-Level Netlist (EDDM format)
Std. Cell Layouts
Mentor Graphics IC Station (adk_ic)
Floorplan Chip/Block
Libraries
ICblocks
Place Route Std. Cells
Process Data
Design Rules
Design Rule Check
Backannotate Schematic
Generate Mask Data
Layout vs. Schematic Check
Calibre
Calibre
Calibre
IC Mask Data
Mach TA/Eldo Simulation Model
37
Cell-Based IC
38
Cell-Based Block
39
Basic standard Cell layout
Source Weste CMOS VLSI Design
40
Preparation for Layout

• Use Design Architect-IC to convert Verilog
  netlist to Mentor Graphics EDDM netlist format
• Invoke Design Architect-IC (adk_daic)
• On menu bar, select File gt Import Verilog
• Netlist file count4.v (the Verilog netlist)
• Output directory count4 (for the EDDM
  netlist)
• Mapping file ADK/technology/adk_map.vmp
• Open the generated schematic for viewing
• Click Schematic in DA-IC palette
• Select schematic in directory named above (see
  next slide)
• Click Update LVS in the schematic palette to
  create a netlist to be used later by Calibre
• Create design viewpoints for ICstation tools
• adk_dve count4 t tsmc035 (V.Ps layout,
  lvs, sdl, tsmc035)
• Can also create gate/transistor schematics
  directly in DA-IC using components from the ADK
  library

41
DA-IC generated schematic
42
Eldo simulation from DA-IC

• Run simulations from within DA-IC
• Eldo, ADVance MS, Mach TA
• DA-IC invokes a netlister to create a circuit
  model from the schematic
• SPICE model for Eldo Mach TA
• Eldo analyses, forces, probes, etc. same as SPICE
• View results in EZwave or Xelga

43
Eldo input and output files
-Netlist -Simulation cmds -Stimulus
44
SPICE netlist for modulo7 counter
SPICE circuit file generated by DA-IC
From ADK library
Force values (created interactively)
45
Force functions (1)

• DC value
• Vsigname A 0 DC 5

Value (volts)
V indicates voltage
Between circuit nodes A and GND (node 0)
Force name
46
Force functions (2)

• Pulse/square wave
• Vsigname B 0 pulse 0 5 0 0.1N 0.1N 20N 40N

Rise Fall time time tr tf
Nodes
Initial Voltage v1
Pulse Period width tp tw
Pulsed Voltage v2
Delay from start of period for waveform to begin
- td
tp
v2
v1
td tr tw tf
47
Force functions (3)

• Pattern wave (for logic 0 1 values)
• Vname B 0 pattern 5 0 5n 0.1n 0.1n 10n 011010 R

Bit pattern
Rise Fall Time between changes
Logic 1 0 voltages
Between circuit Nodes B GND (node 0)
Duration of bit value
Delay to waveform begin
Repeat the pattern (optional)
1
1
1
0
0
0
delay
pattern
48
Eldo simulation of modulo7 counter(transient
analysis)
49
Create a std-cell based logic block in IC Station

• Invoke adk_ic
• In IC Station palette, select Create Cell
• Cell name count4
• Attach library ADK/technology/ic/process/tsmc035
  
• Process ADK/technology/ic/process/tsmc035
• Rules file ADK/technology/ic/process/tsmc035.rul
  es
• Angle mode 45
• Cell type block
• Select With connectivity
• EDDM schematic viewpoint count4/layout
• Logic loading options flat

50
Create Cell dialog box
51
Auto-floorplan the blockplace route gt autofp
52
Auto-place the std cellsAutoplc gt StdCel
53
Auto-place ports (Autoplc gt Ports) Signal
connections on cell boundaries
54
AutoRoute all nets(hand-route any unrouted
overflows)
Then Add gt Port Text to copy port names from
schematic for Calibre
55
Layout design rule check (DRC)

• Technology-specific design rules specify minimum
  sizes, spacing, etc. of features to ensure
  reliable fabrication
• Design rules file specified at startup
• Ex. tsmc035.rules
• From main palette, select ICrules
• Click Check and then OK in prompt box
• (can optionally select a specific area to
  check)
• Rules checked in numeric order

56
Common errors detected by DRC

• To fix, click on First in palette to highlight
  first error
• Error is highlighted in the layout
• Click View to zoom in to the error (see next)
• Example DRC9_2 Metal2 spacing 3L
• Fix by drawing a rectangle of metal2 to fill in
  the gap between contacts that should be connected
• Click Next to go to next error, until all are
  fixed
• NOTE There can be no DRC errors if MOSIS is to
  fabricate the chip they will run their own DRC.

57
Error DRC9_2 metal2 spacing 3L
Draw rectangle of metal2 to fill gap
It also called contact-to-contact metal 2 spacing
DRC9_2 error
58
Layout vs schematic checkCalibre Interactive LVS

• From ICstation menu Calibre gt Run LVS
• In popup, Calibre location MGC_HOME/../Calibre
• Rules ADK/technology/ic/process/tsmc035.calibre.
  rules
• Input count4.src.net (previously created in
  DA-IC)
• H-cells ADK/technology/adk.hcell (hierarchical
  cells)
• Extracted file count4.lay.net
• Compares extracted transistor-level netlist vs.
  netlist saved in DA-IC

59
Post-layout parameter extractionCalibre
Interactive PEX

• Extract Spice netlist, including parasitic RC
• Simulate in Eldo or MachTA
• ICstation menu CalibregtRun PEX
• Options similar to Calibre LVS
• Extraction options
• lumped C coupling caps
• distributed RC
• distributed RC coupling caps
• Output file count4.pex.netlist

60
Post-layout simulation with MachTA

• MachTA is an accelerated Spice simulator
• Digital mixed-signal circuits
• Analyze timing effects pre- and post-layout
• SPICE netlists with parasitic R/C
• Execute test vector file to verify functionality
• Algorithms support large designs
• Partition design, simulate only partitions with
  changes
• Combine time-driven event-driven operation
• Solves linearized models using a proprietary
  high-performance, graph-theory based, matrix
  solution algorithm

61
Mach TA flow diagram
SPICE netlist
ADK/technology/mta/tsmc035
62
Prepare Calibre-extracted netlist for Mach TA
(file.pex.netlist)

• In file.pex.netlist, insert model definitions and
  VDD/GND voltage source functions after comment
  header
• File m7.pex.netlist
• Created Thu Nov 15 152556 2007
• Program "Calibre xRC"
• Version "v2005.2_9.14"
• .model n nmos
• .model p pmos
• Vvdd VDD 0 5
• Vgnd GND 0 0
• Delete (or comment out with in 1st column)
  .subcircuit statement and any continuation lines
  (for long statement)
• .subckt modulo7 CLK Q1 CLEARBAR I1 Q0
  I0 Q2
• L_CBAR I2 GND VDD
• Change .ends to .END near end of file

63
Post-layout simulation with Mach TA

• Invoke Mach TA
• ana - command file to initialize Anacad SW
• mta ezw t ADK/technology/mta/tsmc035 count4.sp
• Other options
• -do file (execute commands from file.do
  instead of design.spdo
• -donot (run without simulating compile
  only)
• -b (run in batch mode no GUI
  output to console)

Transistor calibration files for this technology
Generate waveform database display in EZwave
Netlist, modified as on previous slide
64
Sample Mach TA dofile(transient analysis)
Signals to observe in EZwave

• plot v(clk) v(q2) v(q1) v(q0)
• measure rising TRIG v(clk) VAL2.5v RISE1 TARG
  v(q0) VAL2.5v
• l load
• l reset
• h count
• l clk
• run 5 ns
• h reset
• h clk
• run 5 ns
• l clk
• run 5 ns
• h clk
• run 5 ns

Measure time from rising edge of clk (TRIGger) to
1st rising edge of q0 (TARGet) - voltages
Drive signals low/high (Lsim format)
Simulate for 5 ns
Command to execute dofile file.do
65
EZwave waveform viewer(results for previous
dofile)
Double-click signal name to display.
66
Alternative Mach TA dofile(same result as
previous example)

• plot v(clk) v(q2) v(q1) v(q0)
• measure rising TRIG v(clk) VAL2.5v RISE1 TARG
  v(q0) VAL2.5v
• vpulse Vclk clk 0 pulse(0 3.3 10n .05n .05n 10n
  20n)
• l load
• l reset
• h count
• run 5 ns
• h reset
• run 200 ns

v-levels delay rise fall width period
Nodes to which source connected
Periodic pulses
Voltage source name
67
Mach TA test vector file

• Verify design functionality/behavior
• apply test vectors
• capture outputs
• compare outputs to expected result
• vectors/outputs from behavioral simulation
• Command to execute a test vector file
• run tvend tvfile.tv

test vector file (next slide)
68
Test vector file format

• Test vector file for modulo7 counter
• CODEFILE
• UNITS ps
• RISE_TIME 50
• FALL_TIME 50
• INPUTS clk,reset,load,count,i2,i1,i0
• OUTPUTS q2 (tomax),q1 (tomax),q0
  (tomax)
• CODING(ROM)
• RADIX lt11113gt3
• _at_0 lt01105gtX
• _at_2000 lt00105gt0
• _at_7000 lt01105gt0
• _at_10000 lt11105gt5
• _at_20000 lt01015gt5
• _at_30000 lt11015gt6
• _at_40000 lt01015gt6
• _at_50000 lt11015gt0
• _at_60000 lt01015gt0
• ..

signal order within vectors
Header
Vector format
Sample 5 fs before next vector
Vectors _at_time ltinput_vectorgtexpected_output
Test vectors derived from behavioral simulation
results
69
Behavioral simulation listing
Corresponding Mach TA test vector file
70
Alternate test vector file(clock generated
separately by voltage source)
vpulse vclk clk 0 pulse(0 3.3 10n .5n .5n 10n
20n)
Can mix other simulation commands with test
vector application.
71
Physical Design - FPGA
Component-Level Netlist
Xilinx ISE Altera Max Plus 2
Map to FPGA LUTs, FFs, IOBs
FPGA/PLD Technology Files
Place Route
User-Specified Constraints
Generate Programming Data
Generate Timing Model
Configuration File
Simulation Model
72
SoC Design with Xilinx XPS
Memory
PowerPC
Peripherals