PCI Express Analyzer

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High speed digital systems laboratory
PCI Express Analyzer
A Glance Into The Fast Lane
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Technion - Israel institute of technology
Analyzer Core
Final Presentation
Samuel Amir , Danny Volkind Mr. Orbach Mony
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High speed digital systems laboratory
Agenda

• PCI - Express Reminder
• Link and Lane Training - Overview
• Project Goals
• Project features and capabilities
• PCI-Express Generator - Brief

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High speed digital systems laboratory
Agenda (cont.)

• Project Block Diagram
• Demonstration
• Future Improvement Procedures

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High speed digital systems laboratory
PCI - Express Reminder
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High speed digital systems laboratory
PCI-Express Topology

• Dual Simplex

• Differential

• Speeds of 2.5Gb/sec

TX
RX
TX-
RX-
Device A
Device B
Ref. Clock
Ref. Clock
TX
RX
RX-
TX-
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High speed digital systems laboratory
Packet Formation
Packet formation reflects layered architecture.
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8/10b conversion (4.2.1)

• Convert each byte to a 10bit character according
  to a pre-defined table.
• Extra characters are used as control characters
  or not used.
• Embedded clocking-gt No need to add clock traces.
• Error detection (running disparity).
• DC balancing
• Reduces ISI.

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High speed digital systems laboratory
PCI Express scrambling (4.2.3)

• Assures no constant pattern is transmitted.
• Spread the energy transmitted in one frequency to
  different frequencies-gt reduces EMI! (and gets
  FCC approval)
• Only data characters are encoded.
• Encoding is done using a linear feedback shift
  register.
• Decoding is done using the same process at the
  receiver side.

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High speed digital systems laboratory
Frequency Mismatch (4.2.7)
How does the protocol cope with the fact that
each device is feed by a different clock source?
TX
RX
TX-
RX-
Device A
Device B
Ref. Clock
Ref. Clock
TX
RX
RX-
TX-
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High speed digital systems laboratory
Frequency Mismatch (4.2.7)
Input _at_ 2501MHz Output
_at_ 2500MHz
Input Shift Register is filling up faster than it
is emptied!
Input _at_ 2500MHz Output
_at_ 2501MHz
Input Shift Register is emptied faster than it is
filled!
If we take 600ppm difference between clocks, the
transmitter and receiver clocks can shift one
clock every 1666 clocks!
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High speed digital systems laboratory
Frequency Mismatch-Solution

• The protocol issues a SKIP ordered set that can
  be skipped so that the input shift register can
  be partially cleared!
• The SKIP ordered sets insertion time as dictated
  by the protocol is between 1180 and 1538 symbol
  times.
• Calculated allowed deviance 300ppm !
• This is known as clock tolerance compensation
  mechanism.

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High speed digital systems laboratory
Link Lane Training
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Link and Lane Training
Lane - a single set of differential RX TX pairs
Link - a collection of lanes connecting two
PCI-Express Devices.
x1 Lane wide Link
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High speed digital systems laboratory
Link and Lane Training (cont)
Training - a process aimed at turning a
collection of available lanes into a
properly functioning link.

• Elements established during training
• Physical Level
• SERDES lock.
• Symbol alignment.
• Link Level ? link configuration
• Link data rate
• Link width
• Etc.

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High speed digital systems laboratory
Link and Lane Training (cont)
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Training Ordered Sets

• Group of 16 symbols.
• Used During Polling State (TS1,TS2)
• Establish alignment
• Exchange Physical layer parameters
• Not scrambled!

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Training Ordered Sets (cont)
TS1
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Fast Training Sequence

• Used to re-establish bit and symbol lock when
  transitioning out of the LO power management
  state.

FTS pattern
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High speed digital systems laboratory
Skipped Ordered Set (CTC)
Compensate for differences in frequencies between
bit rates at two devices sharing a mutual Link
(Clock Tolerance Compensation)
Skipped Ordered Set pattern
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High speed digital systems laboratory
Electrical Idle

• Steady state condition
• Transmitter differential pair held at fixed
  value
• Must remain at this state at least 20nsec
• Must attempt to detect a receiver within 100msec

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DLLP packet
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TLP packet
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Packet Header
Header
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Project Goals
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Project Goal Overview

• PCI-Express packets capturing at wire speed of
  2.5Gbps
• Selective filtering work modes
• TLP analysis header based filtering
• Simple register based user interface
• RS232 accessible.

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Project Features Capabilities
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Project features

• Receiving PCIe communication at 2.5 Gbps.
• Full line synchronization capability according
  to PCIe spec.
• Handling of realignment and clock tolerance
  compensation events on the fly.
• Invalid symbol filtering.

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High speed digital systems laboratory
Project features (cont.)

• Detection of and field extraction for all PCIe
  training sequences.
• Selective descrambling of the received data.
• Accumulative user-controlled counters for
  statistic purposes.
• Data stream marking and preliminary analysis.

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Projects features (cont.)

• 6 Available work modes
• Wire Speed Capture.
• Capture TS1 / TS2
• Capture DLLP
• Capture TLP
• Selective TLP capture

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High speed digital systems laboratory
Projects features (cont.)

• TLP filtering versatility

TLP Type field 5 Bit
TLP format field 2 Bit
TLP Traffic Class 3 Bit
TLP length 10 Bit
TLP Attribute 2 Bit
TLP Tag 8 Bit
TLP Byte Enables or Message 8 Bit
TLP Sequence num 12 Bit
TLP Bus num 8 Bit
TLP device number 5 Bit
TLP function number 3 Bit
TLP poisoned packet 1 Bit
TLP Type field Mask 5 Bit
TLP format field Mask 2 Bit
TLP Traffic Class Mask 3 Bit
TLP length Mask 10 Bit
TLP Attribute Mask 2 Bit
TLP Tag Mask 8 Bit
TLP Byte Enables or Message Mask 8 Bit
TLP Sequence num Mask 12 Bit
TLP Bus num Mask 8 Bit
TLP device number Mask 5 Bit
TLP function number Mask 3 Bit
TLP poisoned packet Mask 1 Bit
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Project features (cont.)

• Storage
• Fully user controlled dynamically allocated
  16K x 32 memory.
• Captured data is saved with preliminary
  analysis.
• Bursts and capture events are separated
  allowing selective extraction.

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High speed digital systems laboratory
Project features (cont.)

• LCD Interface
• Built-in LCD micro-controller implementation.
• 1 Kbyte user memory for display commands.
• Display file can be loaded on the fly.

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Project features (cont.)

• User Interface
• RS232 serial link operating at 115.2Kbps.
• Simple comm. protocol implementation allowing
  read and write commands accessing 32bit address
  space with 16bit data.
• All the core features are accessible.

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Generator - Overview

• Capable of generating all PCIe traffic.
• Fully user-controlled.
• PCIe compatible including clock tolerance
  compensation simulation.
• Can be set to continuous or single shot mode.

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High speed digital systems laboratory
Generator - Overview
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Basic Block Diagram
Physical
Physical
3
4
7
Transaction
2
5
8
Physical
1
6
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High speed digital systems laboratory
Top Level
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Project Block Diagram
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High speed digital systems laboratory
PDM LFSR
8 bit values generated by LFSR for repeated data
value of 0
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PDM LFSR (cont)
Scrambling spectral power distribution for
repeated data value of 0
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High speed digital systems laboratory
PDM LFSR (cont)
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High speed digital systems laboratory
PDM LFSR (cont)
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Demonstration
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Future Developments

• Additional functions.

• User interface development.

Open Code flexibility opens the door for
development
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Closing Words
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Additional information
Certain images adopted from PCI-SIG PCI Express
Architectural Overview Presented at the 2002
PCI-SIG Developers Conference and Intel
Developers Forum, Fall 2001.
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High speed digital systems laboratory
Project Development Process
Semester A
Semester B
High Speed Communication Fundamentals
Constructing Analyzer Core Building Blocks
PCI Express Architecture Concepts
Debugging Testing Each block
market survey Current Available Products
Final Core Integration
Existing Infrastructure
Analyzer Core Development report
Final Concept Requirements Doc