Power Amplifier Design

1
Power Amplifier Design
TriQuint MMIC Design Training
AWR Confidential
2
Summary

• An Example of a 2.5 GHz Amplifier to Show
• Setting hotkeys and customizing the AWRDE
• Creating and editing schematics and layouts
• Using TriQuint DRC and LVS
• Simulation and tuning
• Optimization and using statistics
• Nonlinear noise analysis and contributors
• Routing iNets
• Automated Circuit Extraction (ACE)
• Axiem
• System analysis

3
Slide Notation

• This class is a step by step tutorial on the AWR
  Design Environment.
• Complete instructions are provided in the text
  and in the screen shots / pictures on each slide
• The graphic below is always shown on slides where
  there is interaction with the Project, Elements,
  or Layout tabs of the AWR project manager. The
  correct tab for the required action is always
  selected indicating to the user where the items
  they are looking for are located.

4
2.5 GHz PA Amplifier Target Design
5
Target Design

• 3-D view of the target design

6
Loading Libraries (PDKs)
7
Libraries - Installing

• Before using a PDK (Process Design Kit), it must
  be installed on your computer (this procedure is
  how all PDKs in the AWRDE are installed)
• Browse to the installer file (TQOR_TQPEDi_1_1_2x_x
  x.msi) in the folder that was provided to the
  class and run the installer
• Accept all the default settings

Note Your PDK version number will be different.
8
Libraries

• Start the AWRDE and read in a process definition
  by choosing File gt New With Library gt TQOR_TQPED
• If you already had other versions installed, you
  can choose the specific version of the PDK you
  would like to use

9
Project Save

• Save your project using File gt Save Project As
• Choose any project name

10
Project Frequencies

• Go to Options gt Project Options
• Click on the Frequencies tab
• Enter 2.5 for the Start frequency and check the
  box next to Single Point
• Click Apply before clicking OK

11
Setting Hotkeys
12
Hotkeys

• Add a couple of custom hot keys by choosing Tools
  gt Hotkeys

• Note We can customize
• Hotkeys
• Toolbars
• Menubars

13
Hotkeys - 2

• For Categories, choose Window and then select
  WindowTileHorizontal
• Click in the Press the new hotkeys field and
  then press the H key
• Leave Standard as the editor
• Press the Assign button
• Also assign the V key to WindowTileVertical
• Also assign the R key to EditRotateRight
  (under Edit category)

Note You can use the Shift, Ctrl, and Alt keys
in addition to letters to make a hotkey.
14
Creating And Editing Schematics
(Unified Database / Editing Layouts)
15
New Circuit Schematics

• Go to the Project tab and make a new circuit
  schematic named IV_Test by right-clicking on
  Circuit Schematics and choosing New Schematic

Note It is generally a good idea not to use
spaces, esp. with artwork cells. Use the
underscore _ instead.
16
Layout View of Schematic

• Open the layout view of the schematic by clicking
  on the View Layout button

Note There are several toolbar menus - RC in a
blank spot of the toolbar browser area to see the
choices.
Equations Toolbar
Schematic Design Toolbar
Standard Toolbar
Tip There is a Schematic and Layout view
associated with every circuit schematic.
17
Clean Workspace

• Tile the schematic and layout views by using the
  new H hotkey (or select Window gt Tile
  Horizontal)

Note You can change the color of the layout
background using a built-in script Scripts gt
Global Scripts gt Examples gt Toggle_Layout_Color
18
Element Placement

• Elements are found on the Elements tab
• Element categories appear in the top of the pane,
  elements appear in the bottom
• Elements are placed by dragging from the bottom
  pane to the schematic and then letting go of the
  mouse this pulls up a ghost image that can then
  be placed

Elements tab
19
Element View

• Like Windows Explorer, the element view can be
  changed by right-clicking in the lower pane of
  the Elements tab Show Details is a common
  setting.

Tip You can get help on any element by RC gt
Element Help.
Tip The classification of the elements in the
element browser is the same as in the Element
catalog.
20
Element Placement

• Elements can also be placed using the Element
  button
• You can also use the built-in hotkey Ctrl L
• This will bring up the Add Circuit Element
  dialog
• With this dialog, you can find an element by
  typing in its name or searching by keyword in the
  description

Note Use Ctrl click on the column header to
change the field on which you search
21
Element Rotation

• Prior to placement, elements can be rotated with
  the right mouse button

• Tip You can also flip the elements about their
  horizontal axes using
• Horizontal axis - Shift right mouse button.
• Vertical axis - Ctrl right mouse button.

22
Element Categories

• Elements for this exercise can be found in the
  following categories Libraries gt TQOR TQPED
  gt PHEMT gtTOM3 gt PHEMT_Instances gt
  TQPED_EHSS_T3_Inst MeasDevice gt IV gt
  IVCURVE
• Ports, Grounds, and Subcircuitscan be found on
  the tool bar (Schematic Design Toolbar)

• Tip Hot Keys
• Port CtrlP
• Ground CtrlG
• Subcircuit CtrlK

23
Test Bench Assembly

• Assemble the schematic shown below

Note The circled parameters are NOT using
default values. Watch the schematic layout as
you change the W and NG parameters.
24
Test Bench Assembly
25
Creating Graphs and Adding Measurements
(Using Simulation)
26
Adding Graphs

• Add a new rectangular graph named IV_Curves by
  right-clicking on Graphs and choosing New Graph

27
Adding Measurements

• Add a new measurement to the graph by
  right-clicking on the graph and choosing Add
  Measurement
• Choose Measurement Type Nonlinear gt Current and
  Measurement IVCurve and note that it points to
  IV_Test

28
Duplicating Measurement - Aplac

• Copying measurements is a quick way to add
  similar measurements to the same graph or other
  graphs
• You can copy a measurement by dragging an
  existing measurement onto the top of the graph
  icon
• This method of copying works with Schematics,
  Data Files, System Diagrams, Optimization Goals,
  Yield Goals, EM Structures, etc.

29
Duplicating Measurement - Aplac

• Once the Measurement copy is created, it can be
  edited by double-clicking on it
• Change one of the IVCurve measurements so that it
  uses the APLAC DC simulator and click OK

30
Simulation

• Press the lightening bolt (Analyze) button to see
  the results.

31
Using Tuning
32
Tune Setup

• Tune on the circuit by going back to the IV_Test
  schematic window and using the Tune Tool to
  select the W and NG parameters on the eHEMT.
• Once a parameter is selected for tuning it will
  turn blue

Use tune tool to select parametersfor tuning.
Equations Toolbar
33
Tuning

• Press the Tune button and use the sliders to vary
  W and NG and see the effect on the simulation
  results on the graph.

Note The Aplac and standard HB results change
simultaneously
34
Tuning

• Open the layout view of the IV_Test schematic
• Also open a 3D layout view by clicking on the
  View 3D Layout button
• Use your Tile Horizontal or Tile Vertical hotkeys
  to tile all four windows
• Now tune on W and NG to see all four windows
  update simultaneously
• Hold down the Ctrl key to see the layout views
  update real time

35
Tuning
36
Markers and Traces

• Makers can be added to graphs by right-clicking
  on the graph and choosing Add Marker
• The built-in hotkey for this is CtrlM
• Add a marker at 4V VDS and 240 mA IDS
• You can search for a specific point on a graph by
  right-clicking on the marker text and choosing
  Marker Search

37
Markers and Traces

• If we select the trace where 4V, 240mA lies and
  hold down the mouse button, we can see the gate
  voltage on the bottom left of the screen

38
Building the Amplifier
39
Create a New Schematic

• Create a new schematic and name it 1Stage_Amp
• This schematic will need the following elements
  that can all be found under Libraries gt TQOR
  TQPED
• Capacitors gt Lumped gt TQPED_CAPA (x3)
• PHEMT gtTOM3gt PHEMT_Instances gt TQPED_EHSS_T3_Inst
  (x2)
• Resistors gt Lumped gt TQPED_RESW (x6)
• Spirals gt TQPED_MRIND (x1)
• Vias and Pads gt TQPED_SVIA (x3)
• Vias and Pads gt TQPED_PAD (x3)
• These are standard elements
• Ports gt Port (x2) (Can also use CtrlP)
• Ports gt PORT_NAME (x1)

40
1Stage_Amp Schematic Full View
Note The orientation of the capacitors is
important. Look at the \ on the symbol - that
is pin 1.
41
1Stage_Amp Schematic Resistor Bank
Hint Use your new hotkey R torotate the
elements after placing them. Also, use copy and
paste for multiple elements that are the same.
42
1Stage_Amp Schematic Active Bias
43
1Stage_Amp Schematic Active Bias
See next slides for details onsetting inductor
parameters
44
Secondary Parameters

• You will need to modify some of the secondary
  parameters of the inductor
• Right-click on the inductor symbol and choose
  Properties
• Click on the Show Secondary button to expose all
  the parameters
• You will need to add a PIN_ID parameter to Port 2
  called RF_OUT

45
Secondary Parameters

• Make sure the parameters of your inductor match
  these

46
Schematic Layout - Placement
47
Amplifier Layout

• We want to make the layout snap 0.1 um
• Choose Options gt Layout Options
• Change the grid spacing to 0.1 um

48
Amplifier Layout

• Open the layout view of the 1Stage_Amp
  schematic. It might look something like this (a
  mess)

49
Importing GDSII Libraries

• Import a GDSII library into AWRDE by switching to
  the Layout tab and right-clicking on Cell
  Libraries gt Import GDSII Library
• Import Class_Lib.gds from your Training folder

50
Amplifier Layout

• With your schematic layout view open, click on
  the Layout tab and click on the Cell Library
  called Class_Lib
• Toward the lower left corner, you will see a
  Layout Cell called Class_Lib
• Drag this cell into the layout window

Click here
Then drag from here
51
Amplifier Layout

• The schematic layout should now look like this

52
Amplifier Layout

• Place all your components so they match the
  footprints given in the artwork cell (use Ctrl
  key while dragging to enable snap models)
• This will be demonstrated
• You will notice that you end up missing three RF
  OUT bondpads

53
Vector Instance

• Open the schematic view of the amplifier
• Right click on the TQPED_PAD called RF_OUT and
  choose Properties
• Click on the Vector tab and enter 03

54
Vector Instance

• After creating a vector instance the schematic
  wire will default to be a bus instead of a
  wire. This is not what we want as all the bond
  pads should be shorted to each other, not
  connected to individual bus lines.
• Busses are denoted by thick wires
• Double-click on the wire name to edit and change
  it from B103 to B1

55
Vector Instance

• Open the layout view of the schematic, and you
  will now see 4 instances of the RF_OUT bond pad
• Place these appropriately
• When finished, select the footprint artwork cell
  and delete it (Ctrl Shift in conjunction with
  Left Mouse Click provides cycle select
  capability, which might be needed to select the
  artwork cell).
• The layout should now look something like this

56
Associating Artwork with Schematic Elements

• Open the schematic view of the amplifier
• Open the properties dialog of Port 2
• Click on the Layout tab and select RECT_PIN

57
Associating Artwork with Schematic Elements

• Open the layout view of the amplifier
• Find the layout for Port 2, right-click on it and
  select Shape Properties
• Change the Line Type to Metal2

58
Associating Artwork with Schematic Elements

• Move and stretch the RECT_PIN so it encompasses
  all the RF_OUT pads
• To stretch the RECT_PIN, double-click on it to
  bring up the drag handles
• Use the Ctrl key to snap the corners of the
  RECT_PIN to the corners of the pads

59
Associating Artwork with Schematic Elements

• Repeat the same steps for both the PORT 1 and
  VG_CHIP elements, this time using the RECT_PIN
  layout to overlap their corresponding
  individual TQPED_PAD layouts
• This time leave the Line Type at Metal0 in the
  Shape Properties dialog
• Hold down Ctrl to snap to corners

60
Adding Text to Layout

• Open the schematic view of the amplifier
• Click on the Elements tab
• Browse for TQPED_TEXT under Libraries gt TQOR
  TQPED gt Shortcuts gt Text
• Drag the TQPED_TEXT element into the schematic,
  and edit the parameters to match what is below

61
Adding Text to Layout

• Open the layout view of the amplifier
• Put the text wherever you like

62
Changing Layout Parameters

• It is possible to change some parameters of
  certain PDK elements that only affect their
  layout
• Right-click on the large cap on the bottom left
  of the amplifier and select Shape Properties
• Click on the Parameters tab and change M1Top from
  0 to 1 . Notice how the layout changed.
• Do the same for the other two caps

63
Changing Layout Parameters

• We also want to change some of the shape
  properties of the larger eHEMT device.
• Change DFING_LT, SFING_LT, and DPAD_LT from 0
  to 2
• Change GPAD_LT from 0 to 1

64
Schematic Layout - Routing
65
iNet Routing

• iNets are intelligent paths that can be used to
  draw electrical connectivity in layout
• The linetype and default width of the iNet is
  controlled in the Routing Properties dialog
• Bring up this dialog by clicking on the Show
  Routing Properties button

66
iNet Routing

• Change the default width to 70 um and make sure
  the Line type is set to Metal0
• To activate the iNet routing mode, double-click
  on any red ratline

67
iNet Routing

• To start routing, left-click at the center of the
  RF_IN pad (the cursor will snap to the center of
  the pad)
• Move the mouse to the left and double-click on
  the center of the nearest capacitor

68
iNet Routing

• Notice when the route is complete, the ratline
  disappears
• Repeat this procedure by connecting the two
  smaller capacitors with a 70um net on Metal1
• To change the line type mid-route, hit CtrlShift
  and roll the mouse wheel
• Then connect the center capacitor to the larger
  capacitor with a 70um net on Metal0.

69
iNet Routing

• Continue routing until you have a layout that
  looks something like this

70
Shape iNets

• For the traces that connect the large eHEMT to
  the rest of the MMIC, instead of using standard
  iNets, we will use shape iNets
• Draw a rectangle on Metal1 that connects the gate
  of the device to the inductor and the HVR
  resistor
• To draw the rectangle, first click on the Layout
  tab and select the Metal1 draw layer.
• Next, click on the Draw Rectangle button and draw
  the rectangle.

71
Shape iNets

• The rectangle should look like this

72
Shape iNets

• While holding down Shift, select the rectangle
  and one of the ratlines.
• Then right-click and select Associate Net Routes
• Notice that the ratlines disappear

73
Shape iNets

• Repeat the same procedure for the drain
  connection, but this time draw a 6-sided polygon
  using the Draw Polygon button
• This time use Metal2

Hint Use the Ctrl key to snap to vertices.
74
Shape iNets

• This is what the completed layout should look
  like. There should be no ratlines.

75
Schematic Layout - Verification
76
Verification

• Run a quick DRC / LVS on this complete design
• Choose Scripts gt Global Scripts gt
  Run_TQOR_ICED_v8

77
Verification - DRC

• Start by browsing to the paths of ICED and the
  TriQuint verification project (should be the same
  as shown below).
• Choose ICED DRC only (note that mailDRC is
  supported).
• Press OK

78
Verification - DRC

• After the DRC is complete the errors will appear
  in the AWRDE DRC Error Viewer.
• Tile out the DRC error window and the Layout
  Window.
• If desired, double-click on errors to zoom in on
  them.
• When finished choose DRC gt Clear DRC errors.

79
Verification - LVS

• Re-run the script, this time choosing ICED LVS
  only.
• Note that all paths and options are remembered on
  subsequent runs so browsing is not necessary.
• Click OK

80
Verification - LVS

• After the LVS is complete the errors will appear
  in the AWRDE LVS Error Viewer, which cross probes
  between the schematic and layout.
• Tile out the LVS error window, the Layout Window
  and the Schematic Window.
• When finished chose DRC gt Clear LVS errors.

81
Load Pull Analysis
82
Load Pull

• Create a new schematic called Load_Pull
• We want to place an instance of 1Stage_Amp into
  the Load_Pull schematic.
• To insert a subcircuit into a schematic, either
  press the Subcircuit button or use
  CtrlK

83
Changing Symbols

• We want to change the symbol for the 1Stage_Amp
  subcircuit to something more meaningful
• Right-click on the 1Stage_Amp subcircuit, and
  choose Properties
• Click on the Symbol tab
• Change the number of nodes to 2 and click on
  AMP_at_system.syf in the list of symbols

84
Load Pull

• Create the schematic shown below
• Use CtrlL to find the elements by the element
  name

Hint This element is an NCONN,and NCONN names
are case-sensitive
85
Global Definitions

• VG and VD need to be defined, and since they will
  most likely be used in more that one place, it
  will be easiest to define them globally
• Double-click on Global Definitions in the Project
  browser.
• Click on the Equation button to enter values for
  VG and VD
• When entering equations, if you click ShiftEnter
  you can enter the next equation on a new line

Note Variables are case-sensitive
86
Adding DC Annotations

• To make sure the active device is being biased
  properly, we need to add DC annotations
• With the Load_Pull schematic open, click on the
  Annotation button
• This will bring up the Add Annotation dialog
  which is very similar to the Add Measurement
  dialog
• Select DCIA and click Apply
• Select DCVA_N and click OK
• Dont forget to change the simulator to Aplac DC

87
DC Annotations

• Click on the Simulate button to make the DC
  annotations appear on the schematic
• Select the 1Stage_Amp subcircuit and click on
  the Edit Subcircuit button to descend into the
  subcircuit
• Note that the annotations are also included in
  the subcircuit

88
Load Pull Wizard

• In order to conduct load pull, there must be a
  measurement for the parameter we are trying to
  optimize
• Add a rectangular graph called LoadPull Pout
  and add the following measurement to it. We are
  going to use APLAC.

Make sure this is PORT_2
Change simulator to Aplac HB
Dont forget to check dBm
89
Load Pull Wizard

• To start the Load Pull Wizard, expand the Wizards
  node in the Project browser and double-click on
  AWR Load Pull Wizard
• You will get this dialog

90
Load Pull Wizard

• Click on the Add button to choose a measurement
• We only have one measurement, so the choice is
  easy
• Name the data file Pout_Data
• Change the Center Mag to 0.5, the Center Ang to
  180, and the Radius to 0.4
• Click on Coarse and click Set Center and Radius
  (very important)
• The Smith Chart will update to show the points
  that will be swept

91
Load Pull Wizard

• Click Simulate to start the load pull sweep

92
Load Pull Wizard

• When the simulation is complete, you will see a
  Smith Chart with load pull contours
• To get rid of extra contours, right-click on
  the graph, choose Modify Measurement, select the
  LPCS measurement, and increase the Contour Min
  value to 23 or 24
• You may also want to change the Countour Step to
  0.25

93
Load Pull Wizard

• Add a measurement to the Smith Chart called
  LPCSMAX and click Simulate to update the plot
• Add a marker to the LPCSMAX point

94
Re-Normalizing Graph

• To get a more meaningful impedance value from the
  Smith Chart, the graph needs to be re-normalized
  to 50 Ohms
• Open the graph properties dialog and click on the
  Markers tab
• Change Z or Y display to be Denormalized to 50.0
  Ohms

95
Re-Normalizing Graph

• Now click on the Traces tab and change the weight
  of the second trace to make the marker more bold

96
Load Pull Wizard

• The marker will look like this after
  de-normalization

97
Creating And Editing Schematics (Part 2)
Simple Output Match
98
Populating a New Schematic

• Create a new schematic called Output_Match.

99
Tuning the Output Match

• Add an S11 measurement of the Output_Match
  circuit to the Load Pull Data Contour Graph

100
Tuning the Output Match

• Simulate, and the graph should look like this

101
Nonlinear Simulation
102
Adding Subcircuits

• Create another new schematic called
  Packaged_Amp
• Associate the new schematic with the AWR_Module
  LPF
• Insert 1Stage_Amp and Output_Match
  subcircuits into the schematic

103
Approximating Bondwires

• Change the symbol for the 1Stage_Amp subcircuit
  like we did before
• Now we want to add equivalent bondwire models to
  the schematic using the SRL elements (Elements gt
  Inductors gt SRL)
• Change the R and L values of the SRL element to
  match what is below
• This element is called NCONN and is located under
  Interconnects

104
Nonlinear Test Bench

• Create a new Schematic named Power_Sweep
• Insert the Packaged_Amp subcircuit and change
  the symbol to look like a two-port amp
• Populate the schematic so it looks like this

Dont forget quotation marks.
Pin must be explicitly defined.
105
Nonlinear Test Bench

• Add DC voltage and current annotations to the
  Power_Sweep schematic
• Click on the Packaged_Amp subcircuit, and click
  the Edit Subcircuit button
• Click on the 1Stage_Amp subcircuit, and click
  the Edit Subcircuit button again
• Zoom in on the active device to make sure it is
  biased properly

106
Nonlinear Measurement

• We now want to create a plot of Pout vs Pin
• Create a new rectangular graph called Power
  Sweep
• Add the following measurement to the graph

107
Nonlinear Measurement

• Click Simulate and your graph should look like
  this
• Duplicate the Pcomp measurement using the drag
  and drop technique

108
Nonlinear Measurement

• Modify the new measurement to measure power gain

These are NOT the default values
109
Nonlinear Measurement

• Simulate, and your graph will look like this

110
Plotting One Measurement Vs Another

• To plot Gain vs. Output Power first make a new
  rectangular graph and then add the measurement
  shown below.
• The PlotVs Measurement makes it easy to plot
  any single measurement vs. another.
• In this case the plot uses the existing Output
  Power and Gain measurements.

111
Plotting One Measurement Vs Another

• The PlotVs plot is shown below.

112
Using MPROBE

• AWR has a unique measurement probe called MPROBE
  that allows the user to make virtually any kind
  of measurement on their circuit and have the
  results update real-time
• Open the 1Stage_Amp circuit and place an MPROBE
  at the gate of the output eHEMT
• To place an MPROBE, click on the Measurement
  Probe button

113
Using MPROBE

• Add a new rectangular graph called Waveforms
• Open the Add Measurement dialog and choose the
  Vtime measurement under Nonlinear gt Voltage
• Choose Power_Sweep as the Data Source Name
• Choose M_PROBE.VP1 as the Measurement Component
• Choose Plot all traces for Sweep Freq and
  choose Pin13 for SWPVAR.SWP1

Note Do NOT click OK before continuing to the
next slide
114
Using MPROBE

• Click Apply, then add the equivalent measurement
  using Itime under Nonlinear gt Current

115
Using MPROBE

• Your graph should look like this

116
Using MPROBE

• Open the Graph Properties and click on the
  Measurements tab
• Click the AutoStack button

117
Using MPROBE

• Your graph will now look like this

118
Using MPROBE

• Now with only the 1Stage_Amp schematic and the
  Waveforms graph tiled horizontally, start moving
  the MPROBE around in the schematic.
• Note the MPROBE must be placed within 1 grid
  space of an element node for it to work

119
Using MPROBE

• MPROBE also has a dynamic mode
• Right-click on the MRPOBE and select Dynamic
  Probe
• Now you can click anywhere in the circuit and
  even ascend/descend hierarchy
• Disable the time-domain measurements when done

120
Nonlinear Noise Analysis
121
Nonlinear Noise Analysis Duplicate Schematic

• Before running Noise Analysis, lets create a
  noise analysis test bench
• Using the same drag and drop technique used to
  duplicate a measurement, duplicate the
  Power_Sweep schematic and rename it to
  Noise_Sweep

122
Nonlinear Noise Analysis NLNOISE Block

• Open the Noise_Sweep schematic and delete the
  SWPVAR block
• Using the Add Element button (or Ctrl L), add
  an NLNOISE block to the schematic

123
Nonlinear Noise Analysis NLNOISE Block

• Modify the NLNOISE block so the parameters match
  what is shown below

124
Nonlinear Noise Analysis NOIS Parameter

• Open the 1Stage_Amp schematic and double-click on
  one of the eHEMT devices
• Click on the Parameters tab and click Show
  Secondary
• Change the NOIS parameter to 1
• Repeat the same steps for the other eHEMT device

125
Nonlinear Noise Analysis - Measurement

• Create a new rectangular graph and name it NL
  Noise
• Right-click on the graph and choose Add New
  Measurement

126
Nonlinear Noise Analysis - Measurement

• Choose NPo_NL_BW under Nonlinear gt Noise
• Select Noise_Sweep as the source
• Change the Measurement Bandwidth to 30e3,
  change the Simulator to APLAC HB, and make sure
  to check the dBm box

127
Nonlinear Noise Analysis - Measurement

• Click Simulate to see the results on the graph

128
Nonlinear Noise Analysis Noise Contributors

• Click Scripts gt Global Scripts gt NL_Noise_APLAC
  (Main)
• Choose Noise Power and Both then click OK

129
Nonlinear Noise Analysis Noise Contributors

• This will run the Nonlinear Noise Contributors
  script through the APLAC native noise simulator
• When the simulation is complete, click on the
  Info tab in the Status window and search for
• Click on the links to bring up lists of the
  nonlinear noise contributors

130
Nonlinear Noise Analysis Noise Contributors

• Disable the Nonlinear Noise Measurement when done

131
Yield Analysis
132
Yield Analysis

• Before running Yield Analysis, we need to import
  a script with a special histogram function
• Click on the Scripting Editor button to open the
  scripting editor
• Right-click where you see your project name in
  the scripting editors Project browser, and
  choose Import
• Browse to Equations.bas in C\Training_Extra\Scrip
  ts
• Close the scripting editor and save the project

133
Yield Analysis

• Before running Yield Analysis, lets trim down
  the number of simulation points.
• Go to the Power_Sweep Schematic and change the
  step size on the Pin sweep to 5.

134
Adding Equations For Histograms

• Add the following equations to Output Equations
  by double-clicking on Output Equations in the
  Project Browser
• Note that 30 is added to Pout to convert from dBW
  to dBm

Output Equation Regular Equations
Note See next slide for details on adding the
Pout Output Equation
135
Adding Equations For Histograms

• When adding the Pout Measurement Equation note
  that the input power sweep is set to Pin 10
  dBm, not Plot all Values

136
Adding Equations For Histograms

• Add the following text and equation to Output
  Equations.
• The YieldHist() function is used to plot yield
  histograms.

137
Adding Graph For Histograms

• Add a Graph called Generate Histogram
• Add a measurement that plots the value of x
  from the Output Equation added on the previous
  slide.
• Note that x by itself has no meaning, but this
  measurement causes the histogram to update during
  each Monte Carlo Iteration.

138
TriQuint Process Yield Analysis

• For TriQuint libraries all yield analysis is
  controlled by the PROCESS block on the Global
  Definitions Page
• Double-click on it to see the different variables
  and their yield analysis setup.

139
Standard Component Yield Analysis

• For all other components, yield setup is done in
  the Element Options dialog, Statistics tab for
  the individual components or substrates.
• For example, set up the series L in the
  Output_Match schematic as a 10 part with
  Gaussian distribution edit as follows.

140
Running Yield Analysis

• Yield Goals are set up the same as Optimization
  Goals used previously, but are under the Yield
  Analysis node.
• They are not required to run yield and look at
  the performance variation.
• Choose Simulate gt Yield Analysis to bring up the
  Yield Simulation control.
• Change the Maximum Iterations to 50 and press
  the Start button.

141
Viewing Monte Carlo Traces

• As the Yield Analysis runs (may take a bit on
  slow training machines and with a power sweep)
  the performance variation is displayed on the
  graphs.

142
Viewing Monte Carlo Traces

• The Graph Properties (right-click on the graph
  and choose Properties) control this display on
  the Yield Data tab.
• Make the changes shown below.

143
Viewing Monte Carlo Traces

• Now the Graph will only show the minimum and
  maximum performance.

144
Plotting Histograms

• Make a new Graph called Pout Histogram
• Add a PlotCol Measurement to this Graph as shown
  below.
• This measurement is plotting the histogram data
  from the YieldHist() equation that is now stored
  in the Pout_10dBm_In data file. Column 1 is the
  input power and column 2 is the output power.

145
Plotting Histograms

• Right-click on the graph, choose Properties,
  click on the Traces tab, and change the Type to
  Histogram
• The data is very coarse because only 50
  simulations were run.

146
Plotting Histograms

• Disable all measurements on the Pout Histogram
  and Generate Histogram graphs by right-clicking
  on the graphs in the Project browser and choosing
  Disable All Measurements

147
Resetting Trace Properties

• Return to any Graph Properties that were adjusted
  and recheck Show traces and All traces on the
  Yield Data tab.
• Click on Clear in the Yield Analysis window

148
Yield Analysis

• Reset the Power_Sweep Schematic SWPVAR block to
  use 1 dB steps.

149
Automated Circuit Extraction (ACE)
150
The EXTRACT Block

• Open the schematic and layout views of the
  1Stage_Amp schematic and tile them
• Insert an EXTRACT block using the element finder
• Change the settings to match what is below

Name of the extracted EM structure Name of the
group of extracted elements Simulator of choice X
and Y grid size Which STACKUP to use (in Global
Defs) Should the extraction happen if this is in
hierarchy?
151
The STACKUP

• Open the Global Definitions
• Double-click on the TQPED STACKUP element
• The Material Defs. tab is where all the different
  materials used in the stackup are defined

152
The STACKUP

• The Dielectric Layers tab defines the thickness
  of each layer and allows you to scale the way
  they are drawn so the 3D view of the EM structure
  is easier to see

153
The STACKUP

• The Materials tab defines the thickness of
  material (conductors, vias, etc)

154
The STACKUP

• The EM Layer Mapping tab defines which EM layer
  each drawing layer maps to, as well as which
  material it uses

155
The STACKUP

• Click on the Line Type tab to see how each line
  type is mapped into the EM structure

156
ACE Extraction Selecting iNets

• Close the Global Definitions window and return to
  the layout view of 1Stage_Amp
• Select the blue iNet connecting the capacitors to
  the spiral inductor
• Right-click and choose Element Properties

157
ACE Extraction Selecting iNets

• Click on the Model Options tab and check the
  box next to Enable
• That means this net is now included in the
  extract group called EM_Extract
• Repeat the same procedure for all the other iNets
  we routed (not the shapes). NOTE You can use
  Shift to multi-select nets

158
ACE Extraction Selecting iNets

• Click once one the EXTRACT block to highlight the
  selected nets in both the schematic and layout
  views

159
ACE Extraction

• Click Simulate and a window will pop up showing a
  2D view of the extracted traces
• Click on the View EM 3D Layout button to get a
  better view of the extracted nets

160
ACE Extraction

• 3D view of extracted nets

161
ACE Extraction 3D Annotation

• Click on the EM Annotation button to bring up the
  Add Annotation dialog
• Choose ERC gt EXT_CKT3D as the measurement
• You can leave the symbol at its default value of
  10e-6, or make it larger so the extracted
  elements are easier to view

162
ACE Extraction 3D Annotation

• Click Simulate and your 3D view will now show the
  extracted components

163
ACE Extraction Coupling

• We may want to include coupling effects in our
  simulation results
• To turn on coupling, open the schematic view of
  1Stage_Amp
• Double-click on the EXTRACT block and click on
  the ACE tab
• Change Max Coupled Dist to 20 um
• Click Simulate, and note the change in the 3D EM
  view

164
ACE Extraction Coupling
165
ACE Extraction

• You can enable and disable the EXTRACT block to
  compare the simulation results with and without
  the traces extracted
• To see a netlist representation of what is being
  extracted, open the Status window and click on
  the link that looks like this
• This will show you a netlist of every element
  that was used in the extracted document

166
EM Extraction Verify Results

• The graphs now show the merged results that
  include the ACE simulations.
• Press Ctrl F on the graph to freeze the traces,
  disable the EXTRACT block on the schematic, and
  re-simulate to compare the results with and
  without the extraction.
• RE-ENABLE THE EXTRACT BLOCK ON THE SCHEMATIC WHEN
  DONE.

167
Electromagnetic Extraction Using Axiem
168
The EXTRACT Block

• Use AXIEM to make a better model for the inductor
• Insert a new EXTRACT block in 1Stage_Amp using
  the Element Finder
• Change the settings to match what is below

Name of the extracted EM structure Name of the
group of extracted elements Simulator of choice X
and Y grid size Which STACKUP to use (in Global
Defs) Should the extraction happen if this is in
hierarchy
169
EXTRACT Frequencies

• Double-click on the EXTRACT block and change the
  settings on each tab. For fast simulation on the
  training machines some simplified settings are
  used.
• Set the Frequencies to go from DC to 12.5 GHz (5
  harmonics) as shown, and dont forget the Apply
  button!

170
EXTRACT Mesh Settings

• Set the Mesh settings as shown

171
EXTRACT Axiem Settings

• Set the Axiem settings as shown

172
Axiem Extraction Selecting iNets

• Similar to adding the nets to the ACE Extract
  group the inductor needs to be added to an
  Extract group.
• Double-click on the inductor in the schematic, go
  to the Model Options tab, enable it for
  extraction and set the Group name to
  EM_Extract_Ind

Double-click
173
Axiem Extraction Selecting iNets

• Click once one the EXTRACT block to make sure
  that it is associated with the inductor.

174
EM Extraction - Axiem

• Now when you simulate, it will kick off an EM
  simulation of the inductor using Axiem
• This will obviously take longer than our ACE
  extraction because it is a full EM simulation
• When it is done simulating, open the 3D view of
  the extracted document
• Add a mesh annotation by clicking on the EM
  Annotation button and selecting Planar EM gt
  EM_MESH_F. Change the Opacity to 0.5.

175
EM Extraction Cut Planes

• With the 3D view of the EM structure open, click
  on the Use cut plane button
• Drag the cut plane to move it, and drag the
  arrows to rotate the plane
• Some of the hotkeys for manipulating the cut
  plane are
• Change cut axis X, Y, or Z
• Flip cut axis Shift X, Y, or Z

176
EM Extraction Verify Results

• The graphs now show the merged results that
  include the ACE and Axiem simulations.
• Press Ctrl F on the graph to freeze the traces,
  disable the EXTRACT blocks on the schematic, and
  re-simulate to compare the results with and
  without the extraction.
• RE-ENABLE THE EXTRACT BLOCK ON THE SCHEMATIC WHEN
  DONE.

177
System Simulation
ACPR and EVM
178
Copying Schematics

• Copy the Power_Sweep schematic by dragging and
  dropping it on the Circuit Schematics node in
  the Project tab.
• Note the new schematic is named Power_Sweep_1

179
Renaming Schematics

• Rename Power_Sweep_1 to System_Test_Bench

180
Making a System Test Bench

• On the System_Test_Bench delete the SWPVAR block
• Replace the PORT1 element with a PORT_PS1
• Set the port power sweep to go from -30 dBm to 10
  dBm in steps of 1 dB

181
New System Diagrams

• Now go back to the Project tab and make a new
  System Diagram named EDGE_Test_Bench by
  right-clicking on System Diagrams and choosing
  New System Diagram

182
Instantiate Module in System

• On the Elements tab find System_Test_Bench under
  Subcircuits gt NL_S and place it on the
  EDGE_Test_Bench.
• This instantiates the module circuit into the
  System Diagram.

183
Build Up System

• Build the remainder of the circuit as shown
  below.

184
ACPR Graph

• Make a new graph named ACPR and add the two
  measurements shown.
• One measurement is high side (250kHz) ACPR and
  one is low side (-250kHz)

185
EVM Graph

• Make a new graph named EVM and add the
  measurement shown.

186
Spectrum Graph

• Make a new graph named Spectrum and add the
  measurements shown
• Note that one measurement is input spectrum
  (TP.IN) and one is output spectrum (TP.OUT).
  Dont forget to check dBm.

187
System Simulator

• Tile the system diagram and graphs as shown and
  press the Run/Stop System Simulators button to
  start a new power sweep

188
Conclusion

• We created a 2.5 GHz Amplifier and learned how
  to
• Set hotkeys and customize the AWRDE
• Create and edit schematics and layouts
• Use TQ DRC and LVS
• Simulate and tune
• Optimize and use statistics
• Use nonlinear noise analysis and contributors
• Route iNets
• Use ACE and Axiem in the extraction flow
• Use system analysis (VSS)