Selective Gate-Length Biasing for Cost-Effective Runtime Leakage Control

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Selective Gate-Length Biasing for Cost-Effective
Runtime Leakage Control

• Puneet Gupta1
• Andrew B. Kahng1
• Puneet Sharma1
• Dennis Sylvester2

http//vlsicad.ucsd.edu http//vlsida.eecs.umich.e
du
1 ECE Department, University of California San
Diego 2 EECS Department, University of Michigan,
Ann Arbor
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Outline

• Introduction
• LGate biasing methodology
• Experiments and results
• Process effects
• Summary

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Introduction

• Leakage significant portion of total power
• High leakage ? short battery life
• VT increase ? Leakage power reduction
• Most common technique Multiple doping profiles
• Our work increase LGate to increase VT
• No additional process steps
• Leakage variability

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Key Idea
? Slightly increase (bias) the LGate of devices
Impact on Leakage and Delay
No circuit performance loss if only non-critical
devices are biased
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Outline

• Introduction
• LGate biasing methodology
• Experiments and results
• Process effects
• Summary

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Methodology

• Extend a standard cell library with biased LGate
  versions of all cells
• Optimize circuit for leakage by using biased
  LGate versions for non-critical cells

• How much to bias by?
• Small bias
• Small leakage reduction beyond 10 biasing
• Preserve pin-compatibility ? Technique can be
  applied post-routing
• Bound cell delay penalty, minimize leakage

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LGate Biasing Granularity

• Given a cell delay penalty, what should the
  biasing for each device in it be?
• Three levels of granularity
• Technology-level
• All devices in all cells have same biased LGate
• Cell-level
• All devices in a given cell type have same biased
  LGate

• Device-level
• All devices free to have independently biased
  LGate
• Simplification In each cell, NMOS devices have
  one gate length and PMOS devices have another

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Outline

• Introduction
• LGate biasing methodology
• Experiments and results
• Process effects
• Summary

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Validation Flow

• Library characterization
• 8 cells, 4 variants of each cell
• Hspice (using autochar)
• Dual LGate circuit optimization
• DUET/TILOS like
• Pick cells on non-critical paths, replace with
  biased variants
• Cells with higher leakage reduction and higher
  slack are replaced first
• Test cases ISCAS 85 combinational alu128

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Leakage Savings
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Outline

• Introduction
• LGate biasing methodology
• Experiments and results
• Process effects
• Summary

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Manufacturability

• Biasing of the order of CD tolerance ?
  printability questionable
• OPC Mentor Calibre with CD tolerance of 2nm,
  lithosimulation using printimage

Printed dimensions of unbiased and biased device
versions of AND2X6 Nominal LGate 130nm, Biased
LGate 136nm
Device Number Gate Length (nm) Gate Length (nm) Gate Length (nm) Gate Length (nm) Gate Length (nm) Gate Length (nm)
Device Number PMOS PMOS PMOS NMOS NMOS NMOS
Device Number Unbiased Biased Diff. Unbiased Biased Diff.
1 125 132 7 126 132 6
2 124 126 2 126 129 3
3 124 126 2 126 129 3
4 121 127 6 124 130 6
5 121 127 6 122 128 6
6 122 128 6 122 128 6
7 125 131 6 124 131 7

• High correlation between drawn and printed LGate

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Leakage Variability
40-55 reduction in spread
Leakage variability estimated with 2000
Monte-Carlo simulations on alu128 ?WID ?DTD
3.3nm (LGate variations assumed to be Gaussian w/
zero correlation)
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Outline

• Introduction
• LGate biasing methodology
• Experiments and results
• Process effects
• Summary

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Summary

• Conclusions
• LGate biasing gives fine control over the
  delay-leakage tradeoff
• LGate biasing reduces leakage in SVT and DVT
  designs
• The approach does not increase process cost, is
  easy to incorporate in existing design flows
• Ongoing work
• Improved biasing-based leakage optimization
  heuristics
• Gate length selection at true device-level
  granularity
• Evaluation of gate length biasing at future
  technology nodes
• Using asymmetry of timing slacks, rise and fall
  transitions to optimize power with LGate biasing

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Thank You!