Dependable Component Based Software for CE Devices

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Dependable Component Based Softwarefor CE Devices

• Robocop Space4U Experiences
• Tutorial at ICCE 2006

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Outline

• Introduction
• Architecture
• Component Model
• Resource Management
• Fault Management
• Real-Time Prediction
• Wrap-Up

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Performance Prediction Frameworkjoint work with
M.R.V.Chaudron

• Objectives
• At the design phase
• Graphically compose an assembly from components
• Predict performance properties of an assembly
• Task latencies
• Number of missed deadlines
• Processor, bus, memory load
• Note without even buying the constituent
  components!

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Real-time Property Prediction Abstract example
CompC
CompB
CompA
CompD
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Application Domains

• Hard real-time systems
• Task lateness leads to catastrophic results
• anti-lock braking system
• air-bag controller
• Firm real-time systems
• No catastrophic consequences, but value of the
  function 0
• car navigation
• surveillance camera
• Soft real-time systems
• Task lateness reduces a value of the function
• multimedia, video and audio codecs
• electronic game

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Case Study MPEG Decoder

• Requirements
• MPEG4 decoder functionality
• Rate of skipped frames lt 1
• Refreshment frequency is 25 frames/sec
• Missing deadline for decoding task lt once per 4
  sec

• Goal without even buying the components
• Assess the performance and timeliness of a
  designed assembly

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Performance Prediction Approach (1/2)

• The approach is a four-step strategy
• The component developer specifies
• behaviour model of a component
• resource model of a component
• Application developer
• composes selected components/services and
• selects scenario of interest models this
  scenario (application scenario model)
• These three models are compiled together
• into a model of the execution architecture (incl.
  concurrent tasks)
• For each scenario the tasks execution is
  simulated
• ?execution timeline of tasks

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Performance Prediction Approach (2/2)
Input
Application requirements
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Characteristics of Models

• Reflect the implementation at higher abstraction
  level
• Behaviour model
• for each operation specifies a sequence of
  invocations of operations of other interfaces
• Resource model
• contains processing, bandwidth and memory usage
  of each component operation
• Application Scenario model
• assembly structure, specific for this scenario
• environmental events or system interrupts (task
  triggers)
• Resource, Behaviour and Scenario models are
  composable
• composed model represents an execution
  architecture (task pool) of a whole application

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Behaviour and Resource Models
BehavourModel_MPEG4Decoder_Component
behaviour operation IDecode.decodeFrame()
calls IBufferAccess.getElement()
passedBits 0 returnedBits 1024
synchronous TRUE
numberOfIterations 1 calls
IBufferAccess.storeElement()
passedBits 1024 returnedBits 1
synchronous TRUE
numberOfIterations 1
ResourceModel_MPEG4Decoder_Component resource
use operation IDecode.decodeFrame()
cpu claim max 1E7 cycles
(reference processor) aver 1E5
cycles (reference processor) min
1E4 cycles (reference processor) mem
claim 10 KB mem release 3 KB
IDecode
IBufferAccess
decodeFrame()
getElement()
storeElement()
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Composing MPEG4 Decoder AssemblyOut of selected
services
IWrite
IRead
IDecode
vRenderer Renderer
vReader Reader
vDecoder MPEG4Decoder
IBufferAccess
IBufferAccess
IBufferAccess
IBufferAccess
IBufferAccess
wBuffer FIFO Buffer
rBuffer FIFO Buffer
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Specifying Scenario Model
Processing Node MIPS 130
IWrite
IRead
IDecode
vRenderer Renderer
vReader Reader
vDecoder MPEG4Decoder
IBufferAccess
IBufferAccess
IBufferAccess
IBufferAccess
IBufferAccess
wBuffer FIFO Buffer
rBuffer FIFO Buffer
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Composing the Models (1/3)
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Composing the Models (2/3)

• The generated task specifies
• sequence of constituent method invocations
• period, deadline, priority, synchronization
  constraints

Service_A
Operation_A
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Composing the Models (3/3)
Task Trigger
IWrite
IRead
IDecode
vRenderer Renderer
vReader Reader
vDecoder MPEG4Decoder
IBufferAccess
IBufferAccess
IBufferAccess
IBufferAccess
IBufferAccess
wBuffer FIFO Buffer
rBuffer FIFO Buffer
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Simulation and Analysis (1/2)
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Simulation and Analysis (2/2)

• Simulation or Schedulability analysis are
  performed with scheduling algorithms deployed on
  the target OS (RMA, EDF, CBS)
• Simulation results in task latencies, number of
  missed deadlines, CPU, memory and bus utilization

Simulation time
Bus load
Mem load
Simulation time
Simulation time
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Validation against Requirements
Video Decoding Task Related REQ Skipped
frames rate lt 1

• Decision on acceptance of the composed assembly
• If not accept try different component
  configurations, or other components
• If accept buy the components, implement
  application-level glue code, test and deploy

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Not mentioned Facilities and Benefits

• Modelling of parameter-dependent behaviour and
  resource usage
• Multiple-platform resource models
• Task synchronization aspects can be modeled
• Component mapping on multiprocessor architecture
• Multidimensional design space exploration
• robusteness vs cost, memory_load vs cpu_load, etc

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Framework Deployment Issues

• We have developed a tool chain supporting the
  design activities
• We have validated the prediction approach by
  MPEG4 Decoder case study
• prediction accuracy of general performance is gt
  90
• prediction accuracy on task latencies is gt 70

Real-Time Prediction Framework
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RTIE Graphical Composer