Chap. 5 Flip-Flops and Related Devices

1
Chap. 5 Flip-Flops and Related Devices

• Introduction
• Combinational Circuit
• The output levels at any instant of time are
  dependent on the levels present at the inputs at
  that time
• Any prior input-level conditions have no effect
  on the present outputs because combinational
  logic circuits have no memory
• Most Digital Systems Combinational circuits
  Memory elements
• General digital system that combines
  combinational logic gates with memory device
  Fig. 5-1
• The external outputs are a function of both its
  external inputs and the information stored in its
  memory elements
• The most important memory element Flip-Flop
• F/F is made up of an assembly of logic gates
• Even though a logic gate, by itself, has no
  storage capability, several can be connected
  together in ways that permit information to be
  stored(Refer to Fig. 5-7, p. 186).
• Output State of F/F Fig. 5-2
• Normal output (Q) 0 or 1 1 HIGH
  Set
• Inverted output(Q) 1 or 0 0 LOW
  Clear RESET
• F/F Latch Bistable multivibrator (Refer to
  Slide 5-16).

2

• 5-1 NAND Gate Latch
• NAND gate latch(or Latch)
• Constructed from two NAND gates Fig. 5-3
• Setting the Latch
• Both cases Q ends up HIGH
• Fig. 5-4
• Clearing the Latch
• Both cases Q ends up LOW
• Fig. 5-5
• Simultaneous Setting and Clearing
• Set Clear 0
• Q 1 Undesired condition
• Set Clear 1
• No change
• NAND Latch Summary
• Fig. 5-6(a),(b)

Normally High Input
Fig. 5-3 2 possible resting state when SETRESET1
Fig. 5-4 Pulsing SET input to 0
Fig. 5-3 ?? Normal rest
1
1
Fig. 5-5 Pulsing CLEAR input to 0
3

• Alternate Representations Fig. 5-7
• Ex. 5-1) Determine Q output in Fig. 5-8
• Ex. 5-2) Switch debouncing circuit in Fig. 5-9
• 5-2 NOR gate Latch
• Ex. 5-3) Determine Q output in Fig. 5-11
• Ex. 5-4) what happen if the light beam is
  momentarily interrupted in Fig. 5-12
• Q will remain HIGH and the alarm will remain ON
  even if phototransistor return to ON( Set0,
  Clear0 no change)
• F/F State on Power-Up
• When power is on, not possible to predict the
  starting state of a F/Fs output
• Output depend on factors such as internal
  propagation delays, parasitic capacitance, and
  external loading.
• To start of in a particular state, activate
  SET/CLEAR input at the start of circuit.

Fig. 5-7 Alternate Representation
0
0
Resting Input 0
Invalid Q 0
0
1
Fig. 5-10 (a) NOR gate latch, (b) truth table,
(c) simplified block symbol
Inactive Stage(Resting ) NAND latch SC1 NOR
latch SC0
4

• 5-3 Troubleshooting Case Study
• Ex. 5-5) Describe analyze the circuit in Fig.
  5-13
• Ex. 5-6) what are the possible faults(refer to
  Tab. 5-1)
• Possible faults(Switch position A?? Q1??? ?)
• Internal open at Z1-1 0? ???? ??
• Component failure in NAND gate Z1
• Internally shorted to ground at Z1-3, Z1-4, and
  Z2-2
• 5-4 Clock Signals and Clocked F/Fs
• Async/Synchronous System
• Asynchronous System The output of logic
  circuits can change state any time one or more of
  the input change
• Synchronous System The exact times at which any
  output can change states are determined by a
  signal commonly called the clock
• Synchronous circuits are easier to design and
  troubleshoot because the circuit outputs can
  change only at specific instants of time.
• Clock Signal rectangular pulse train or square
  wave(Fig. 5-14)
• Positive-Going Transition(PGT), Negative-Going
  Transition(NGT)
• The synchronizing action of the clock signals is
  accomplished through the use of clocked flip-flops

5

• Clocked Flip-Flops Fig. 5-15
• 1. Clocked FFs have a clock input(CLK, CK, or CP)
• In most clocked FFs, the CLK input is
  edge-triggered NGT or PGT
• 2. Clocked FFs have one or more control inputs
• The control inputs will have no effect on Q until
  the active clock transition occurs(Synchronous
  control inputs)
• 3. In summary,
• The control inputs control the WHAT Output
  state(DATA 0 or 1) will go to
• The clock input determines the WHEN actually
  triggers the change
• Setup and Hold Times
• Setup time(5 - 50 ns)
• minimum time that control input must remain at
  constant
• value before the transition.
• Hold time(0 - 10 ns)
• minimum time that control input must not change
• after the positive transition
• 5-5 Clocked S-C F/F
• Clocked S-C F/F
• Waveform analysis in Fig. 5-17 positive going
  edge transition

50
Control Input
Clock Input
Set-Clear F/F
Positive clock transition
ts th
6

• The clock input Trigger input
• Negative-going edge transition Fig. 5-18
• Internal circuitry of the edge-triggered S-C F/F
• Edge-triggered S-C F/F Fig. 5-19
• 1. NAND Latch
• 2. Pulse-steering NAND gate? ?? 1? ???? SET0 ?
  ?? Q1
• 3. Edge-detector Fig. 5-20
• 5-6 Clocked J-K F/F
• Clocked J-K F/F Fig. 5-21
• Toggle Mode J K 1(S-C F/F??? Invalid)
• Negative-going edge transition Fig. 5-22
• Internal circuitry of the edge-triggered J-K F/F
  Fig. 5-23
• Q0, 1? ???? JK1? ????
• NAND 1 ? ??? ?? 1?? ??? ??? 0? ?? Q 1? Toggle
• NAND 2? ??? 1, 1, 0?? ??? ??? 1? ?? 0??
  Toggle
• 5-7 Clocked D F/F
• Clocked D F/F Fig. 5-24
• Implementation of the D F/F Fig. 5-25
• Parallel Data Transfer Fig. 5-26

Jack-King F/F
Data F/F
7

• 5-8 D Latch Transparent Latch
• D Latch Fig. 5-27
• Edge detector is not used EN(Enable) input ??
• Ex. 5-7) Determine waveform Q in Fig. 5-28
• 5-9 Asynchronous Inputs
• Asynchronous Inputs( override inputs)
• Used to set the FF to the 1 or clear the FF to
  the 0 state at any time, regardless of the
  conditions at the other inputs
• Clocked J-K F/F with asynchronous inputs Fig.
  5-29
• Designations for Asynchronous Inputs
• PRE(Preset), CLR(Clear)
• SD(Direct SET), RD(Direct RESET)
• Ex. 5-8) Determine the Q output in Fig. 5-30
• 5-11 F/F Timing Considerations
• Setup/Hold Time
• Propagation Delays Fig. 5-33 (Typ. MAX Few -
  100 ns)
• tPLH Delay going from LOW to HIGH, tPHL HIGH
  to LOW

D Latch is not edge Triggered, (Level Triggered)
Use the overbar to indicate the active LOW
CLK
Q
tPHL
tPLH
8

• Maximum Clock Frequency fMAX(Typ. Max 20 to 35
  MHz)
• Clock Pulse HIGH and LOW Times Fig. 5-34(a)
• The minimum time duration that the CLK must
  remain LOW before it goes HIGH tW(L), and HIGH
  before it returns LOW tW(H)
• Asynchronous Active Pulse Width Fig. 5-34(b)
• The minimum time duration that a PRESET or CLEAR
  input must be kept in its active state in order
  to reliably set or clear the FF
• tW(L) for active-LOW asynchronous inputs
• Clock Transition Times
• Manufacturer usually do not list a maximum
  transition time requirement
• Generally less than 50 ns for TTL, and less than
  200 ns for CMOS
• Actual ICs Tab. 5-2(TTL 7474, 74LS112, CMOS
  74C74, 74HC112)
• Ex. 5-9) Determine following from Tab. 5-2
• (a) tPLH 25 ns for 7474, (b) tPHL 41 ns for
  74HC112, (c) tW(L) for 74LS112, active-LOW CLR
  input, (d) 7474, Hold time is needed(non-zero
  hold time), (e) All F/F, Setup time is needed(No
  non-zero setup time)

9
- ?? ??? ?? ?? - CLK ?? ?? Q1 1 ??, CLK ??? ???
J2 1?? ??? Q2 1

• 5-12 Potential Timing Problem in FF Circuits
• Potential Timing Problem Fig. 5-35
• J2 input of Q2 will be changing as it receives
  the same NGT( ). This could lead to an
  unpredictable response at Q2
• ??? tPHL must be greater than Q2s hold time
  requirement
• Hold time? ?? CLK ??? control input? ?? ???? ??
  ??
• Fortunately, all modern edge-triggered FFs have
  hold time requirements that are 5 ns or less
  most have tH 0(clock transition? ??? control
  input? ???? ??? ??)
• For these FFs, situation like that in Fig. 5-35
  will not be a problem
• ?? FFs hold time requirement is short enough
  to respond reliably
• The FF output will go to a state determined by
  the logic levels present at its synchronous
  control inputs just prior to the active clock
  transition
• if we apply this rule to Fig. 5-35, J2 1, K2
  0
• Ex. 5-10) Determine the Q output in Fig. 5-36
• Clock transition? ?? ?? ?? ???

CLK ??? ??? J2?? 1(Q1) ? ????? ??? J1 K1 1?
?? Toggle?? CLK ??? ??? ??? J2 0? ?? J2? Hold
time? ?? ?? ? ??
10

• 5-13 Master/Slave FFs
• Master/Slave FF
• 2?? F/F? ??(Slave ? Master F/F)?? negative-edge
  transition ??
• ?? ?? ???? ?? Timing Problem ??(Sec 5-12)
• Timing Problem? ?? ??
• Negative Edge triggered F/F ?? ??
• Master/Slave F/F ?? ??? ??
• ??
• 7470 J-K Edge triggered F/F
• 7471 J-K Master/Slave F/F
• 5-14 FF Application
• Unclocked FFs
• Switch debouncing(Ex. 5-2), Event storage(Ex.
  5-4)
• Clocked FFs
• We will briefly introduce the more common
  applications in the following sections

11

• 5-15 FF Synchronization
• Asynchronous signal input
• A human operators actuating input switch at some
  random time
• A FF can be used to synchronize the effect of an
  asynchronous input
• Partial Pulse Fig. 5-37 (Ex. 5-11)
• The operator actuates or releases the switch are
  essentially random, This can produce partial
  clock pulses at output X
• A method for preventing the appearance of partial
  pulses Fig. 5-38 (Ex. 5-11)
• 5-16 Detecting an Input Sequence
• Detecting an Input Sequence Fig. 5-39
• An output is to be activated only when the inputs
  are activated in a certain sequence
• HIGH output only if A goes HIGH and then B goes
  HIGH some time later
• 5-17 Data Storage and Transfer
• Register
• A data(binary number, BCD number,..) are
  generally stored in groups of FFs called
  registers

FF Synchronization
12

• Data Transfer
• The data transfer involves the transfer of data
  from one FF or register to another
• The logic value stored in FF A is transferred to
  FF B upon the NGT of the TRANSFER pulse
• Synchronous data transfer Fig. 5-40
• Asynchronous data transfer Fig. 5-41
• Transfer Enable 0 PRECLR1, ???? FF?? ??
• Transfer Enable 1 A1 ?? B1, A0 ?? B0
• Parallel Data Transfer Fig. 5-42
• The contents of X1, X2, and X3 are transferred
  simultaneously into Y1, Y2, and Y3(Upon
  application of the PGT of the TRANSFER pulse)
• Parallel transfer does not change the contents of
  source register
• 5-18 Serial Data Transfer Shift Registers
• Shift Register Fig. 5-43
• A group of FFs arranged so that the binary
  numbers stored in the FFs are shifted from one FF
  to the next for every clock pulse
• Hold Time Requirement
• In shift register, the FFs must have a very small
  or zero hold time requirement

Sec. 5-12 Timing Problem? ??
13

• Serial Transfer between Registers Fig. 5-44
• Ex. 5-12) The contents of each FF after sixth
  shift pulse in Fig. 5-44 ?
• The registers are filled up with zeros(zero
  inserted)
• Shift-Left Operation
• ??? ??(Shift ??? ?? ???? ???, ?? ??? ?? ??)
• Parallel versus Serial Transfer
• Parallel transfer Speed
• All of the information is transferred
  simultaneously upon the occurrence of a single
  transfer command pulse
• Serial transfer economy and simplicity
• The complete transfer of N bits requires N clock
  pulses
• 5-19 Frequency Division and Counting
• 3 bit binary counter Fig. 5-45
• The FFs change state(toggle) whenever the pulses
  are applied
• Each FF divides the frequency of its input by 2
• Counting Operation Fig. 5-46(State Table)
• State Transition Diagram Fig. 5-47
• Graphical representation of state table
• Circle(state), Line(transition),
  I/O(input/output)

?? ?? Transmission wire ??
N ? FF? 1/2N ?? ?? ??
clock
14

• MOD Number
• MOD Number indicates the number of states
• N Flip-flops 2N different state, and count up
  to 2N - 1
• Ex. 5-13) What will be the state after 13
  pulses(??? 101) in Fig. 5-45
• Ex. 5-14) 6 Flip-flop arrangement of Fig. 5-45
• 5-20 Microcomputer Application
• Transfer binary data of internal register to
  external register X Fig. 5-48
• 1) Place the binary number onto its data output
  lines
• 2) Place the proper address code on its address
  output lines
• 3) Generate the clock pulse CP(Write signal)
• Ex. 5-16) a) What is address decode logic ?
  11111110
• b) address code 11111111? ? X ? X
  will not change(??? 0110)
• 5-21 Schmitt-Trigger Devices
• Schmitt-Trigger Inverter Fig. 5-49
• Schmitt-trigger type of input is designed to
  accept
• slow-change signals and produce an
  oscillation-
• free output (?? Fig. 5-49b)

15

• 5-22 One-Shot(Monostable Multivibrator)
• One-Shot Fig. 5-50(a)
• 1) Once triggered by trigger input(T), Q
  Opposite state
• 2) 1 remains for a fixed period of time
  tp(Determined by tp 0.69RC)
• 3) After a time tp, the OS outputs return to
  their resting state(0)
• Non-retriggerable One-Shot Fig. 5-50(b)
• Retriggerable One-Shot Fig. 5-51
• Actual Devices Fig. 5-52
• 74121/221 Single/Dual non-retriggerable
  one-shot
• 74122/123 Single/Dual retriggerable one-shot
• 5-23 Analyzing Sequential Circuits
• Analyze a sequential circuits(FFs Gates) in the
  following example
• Ex. 5-16) Determine the waveform at X, Y, Z, and
  W for 8 clock cycles
• Counter stops counting at X1, Y0, and Z0(W0
  no change)

Quasi-stable State
?? 0 ?? 1
16

• 5-24 Clock Generator Circuits
• Multivibrator
• Bi-stable multivibrator Flip-flops have two
  stable state
• Mono-stable multivibrator One-shots have one
  stable state(0)
• Astable Free-running multivibrator no stable
  state
• Schmitt-Trigger Oscillator Fig. 5-54
• 555 Timer Used as an Astable Multivibrator Fig.
  5-55
• Ex. 5-17) Calculate the frequency and the duty
  cycle of the 555 timer
• Crystal-Controlled Clock Generators
• Output frequency Crystals resonant frequency
• Clock Generator Circuit 10 kHz 80 MHz ( refer
  to 7 Ed. Fig. 5-58 )
• Using TTL inverter R 300 - 1500 Ohm, ?? 20
  MHz
• Using CMOS inverter R 100 K Ohm, ?? 10 MHz
• 5-25 Troubleshooting FF circuits
• Open Inputs Ex. 5-18
• K0 ? Open ?? J0 K0 1 ? Toggle ?(TTL open 1)

1 Quasi-Stable State
R depends on the type of crystal used and its
frequency(Graph? ???)
17

• Shorted Outputs Ex. 5-19( Fig. 5-57 )
• D(Z2-2)? 0? ????, ??? Q(Z2-5) 0 ??? ??
• Possible Circuit Faults
• Z2-5 or Z1-4 is internally shorted to Vcc
• Z2-5 or Z1-4 is externally shorted to Vcc
• Z2-4 is internally or externally shorted to
  GROUND(Preset Q 1)
• Z2 internal failure
• In case of Z2 internal failure
• 1) Check Z2s Vcc and GROUND O.K.
• 2) Unsoler Z2, and Check its amplitude,
  frequency, pulse width, and transition times
• (by using oscilloscope) O.K.
• 3) Replace it with new one, but the new chip
  behaves in exactly the same way
• 4) Finally he detects a solder bridge between
  pins 6 and 7 of Z2
• 5) Remove the solder bridge and then the circuit
  functions correctly
• Explain how this fault produced the operation
  observed
• The Q and outputs are internally
  cross-coupled so that the level
• on one will affect the other
• A constant LOW at would keep a LOW at one
  input of NAND
• gate so that Q would have to stay HIGH
  regardless of the J or K

??? Q 1
Rule out
1
0
Both outputs should be checked for faults, even
those that are not connected to other devices
18

• Clock Skew
• A clock signal arrives at the CLK inputs of
  different FFs at different times(propagation
  delay? ??)
• The skew can cause a FF to go to a wrong state
  Fig. 5-58
• Q2 ? CLOCK 1?? Q10 ? ???? ?? Q20 ? ??? ?(???
  ????? CLOCK 2 ??? Q21? ?? ???)
• ?? ??
• Problems caused by clock skew can be eliminated
  by equalizing the delays(the active transition
  arrives at each FF at approximately the same
  time)

??? Clock Input??? Propagation Delay? ??
19

• 5-26. Applications using PLD
• CUPL syntax of NAND latch Fig. 5-59
• Q !SBAR !QBAR
• QBAR !CBAR !Q
• CUPL syntax of D latch Fig. 5-27 (p.204)
• Q !SBAR !QBAR (D EN) !QBAR
• QBAR !CBAR !Q (!D EN) !Q
• State transition example Fig. 5-49 (p.226)
• sequence Q2, Q1, Q0 sequence counter_out
• Field counter_out Q2, Q1, Q0 field?
  SETQ2, Q1, Q0 ? ??? ??
• CUPL state transition input file for 3-bit
  counter Fig. 5-60