Small Feature Reproducibility Measuring, Understanding and Controlling Variability in Sub-quarter micron patterning

1
FLCC
Feature-level Compensation Control
Process Integration April 5, 2006
A UC Discovery Project
2
Year 2 Milestones

• Si/Ge-on-insulator and Strained Si-on-insulator
  Substrate Engineering (M28 YII.13)
• Increase thermal robustness of GeOI by
  using nitrogen and ammonia plasma for bonding.
  Use of pseudo-MOSFET structure to evaluate
  transferred layer electronic properties. Develop
  a thermal-mechanical model to predict transferred
  layer thickness and structural stability. Work
  with industrial sponsors to initiate SOI
  research.
• Diffusion of oxygen in germanium (M29 YII.14)
• Determine the diffusion coefficient for
  the diffusion of oxygen in germanium, including
  the temperature dependence and the activation
  energy of the diffusion. Investigate the effect
  of an SiO2 cap on the diffusion of Si in Ge.
  Initial experiments on interaction of fine
  patterns with diffusion.
• Transient enhanced diffusion of B in Ge
  (Milestone added)
• Investigate the effect of ion implantation
  damage on the diffusion of B in Ge.
• Intermixing of germanium in SOI films (YII.15)
• Develop a process for selectively forming
  strained Si1-xGex-in-SOI by intermixing Ge Si

3
Year 3 Milestones

• Si/Ge-on-insulator and Strained Si-on-insulator
  Substrate Engineering (DEV Y3.1)
• Prototype GeOI MOSFET performance
  evaluation. Demonstrate GeSiOI layer transfer
  using GeSi epi wafers. Investigate interfacial
  quality with high-K dielectric as buried
  insulator.
• Effect of surface on diffusion in germanium (DEV
  Y3.2)
• Utilize the test mask for the growth of
  thermal oxide and thermal nitride on Ge to
  systematically study the effects of the surface
  layers on diffusion in Ge.
• Effect of implantation damage on the diffusion of
  dopants in Ge (DEV Y3.3)
• Study the effect of ion implantation, in
  particular, end of range damage on the diffusion
  of common dopants in Ge. Determine if ion
  implantation damages have any transient effect on
  diffusion in Ge.
• Characterization of Si1-xGex formed with Ge/Si
  intermixing process (DEV Y3.4)
• Characterize the resistance of boron-doped
  Si1-xGex-on-insulator formed by the Ge/Si
  intermixing process. Characterize
  metal-to-Si1-xGex-on-insulator contact resistance
  and explore ways of lowering this to below 10-8
  W-cm2.

4
Advanced Source/Drain Technology
Tsu-Jae King
Pankaj Kalra

• Nano-scale CMOS devices technology
• Materials processes
• to improve performance
• and/or scalability of
• logic memory ICs

• Source/drain design process technology for
  nano-scale CMOS
• Joined FLCC program
• in Year 2

• FLCC Research Theme
• Low-resistance source/drain technology for
  thin-body FETs
• Si1-xGex source/drain to lower parasitic
  resistances
• Impact of dopant pile-up and strain on contact
  resistance

5
Motivation
Planar Bulk-Si Structure
Thin-Body Structure
MOSFET scaling to Lg lt 10nm
Double-Gate FinFET

• Si1-xGex in the S/D regions will be
• needed for thin-body PMOSFETs to
• enhance mobility via strain
• lower parasitic resistance
• S/D series resistance
• contact resistance

6
Impact of Process Variations
Z. Guo et al., Intl Symp. Low Power Electronics
and Design, 2005
Comparison of SRAM SNM Distributions

• Mixed-mode MC simulations
• FinFET variations are due to parameter variations
  
• 3?Lg 3?TSi 10Lg
• Bulk-Si MOSFET variations are due to random
  dopant fluctuations only

7
The Problem
CONTACT AREA

• Contact Scaling
• Due to reductions in active area, silicide-to-Si
  contact resistance is now an issue

W Plug
MSix
Si
CMOS FinFET I-V Characteristics

• High Rseries in p-channel thin-body FETs
• limits performance

TSi10nm
F.-L. Yang et al., 2004 Symp. VLSI Technology
8
Approaches to Lowering rc
Kelvin Test Structure (plan view)

• Material engineering
• Si1-xGex source/drain
• Fermi-level de-pinning by interface passivation
• Image-force barrier lowering
• Strain-induced FB reduction

Bending Apparatus
K. Uchida et al., 2004 IEDM
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Formation of Epitaxial Si1-xGex

• The conventional approach (epitaxial growth in a
  UHV-CVD tool) is difficult for ultra-thin body
  FETs
• Thin Si is etched away during the hydrogen
  pre-bake step!
• An alternative approach is to selectively deposit
  Ge by conventional LPCVD, then diffuse it into Si
• GeH4 gas, 340oC, 300mT
• high process throughput

Test Structure to study the intermixing of Ge
with Si (cross-section view)
10
Milestones

• Y2 Formation of Si1-xGex by intermixing Ge with
  Si
• Process variables anneal temperature, time, Ge
  doping
• Y3 Characterization of Si1-xGex formed by
  intermixing
• Parameters Ge and B profiles, resistivity,
  contact resistance
• Investigation of approaches to lower rc to lt10-8
  W-cm2.
• Y4 Fabrication of ultra-thin-body SOI PMOSFETs
  with Si1-xGex source/drain
• Impact on hole mobility and parasitic resistance
• Impact on variability (in on-state and off-state
  currents)

11
Diffusion Studies in Ge and SiGe
Chris Liao, Judy Liang, and Prof. Eugene E.
Haller University of California at Berkeley and
Lawrence Berkeley National Laboratory, Berkeley,
CA
12
Motivation

• SiGe and Ge are utilized in current and new
  generations of electronic devices to enhance
  performance
• Due to aggressive scaling of MOSFET, precise
  dopants profile control is crucial
• Xj lt 10 nm by 2008
• Extension lateral abruptness lt 3 nm/decade by
  2008
• Advanced modeling and control of diffusion
  requires an improved basic understanding of
  diffusion processes in SiGe and Ge

Planar Bulk-Si MOSFET Structure
Courtesy of Pankaj Kalra and Prof. Tsu-Jae King
International Technology Roadmap for
Semiconductors (ITRS), 2005
13
Current Milestones

• Year 3 Milestone (2006) Investigate transient
  enhanced diffusion (TED) effects in Ge
• Determine the temperature dependent equilibrium
  diffusivity of B in Ge (in progress)
• Study the effect of ion implantation damage on B
  diffusion in Ge (in progress)

14
The Problems

• Equilibrium diffusion and non-equilibrium
  diffusion effects are not well understood in Ge
  and SiGe
• Large discrepancies of diffusivity values of
  common dopants in Ge exist in the literature
• Non-equilibrium defect concentrations have been
  shown to enhance (or retard) dopant diffusion in
  Si
• Non-equilibrium transient effects on diffusion in
  Ge and SiGe are in progress

15
Equilibrium Diffusion in Ge

• Diffusion in Ge is believed to be mostly
  vacancy-mediated (contrary to Si, where both
  vacancies and interstitials are involved)
• Interstitials and their effects in Ge have not
  been observed experimentally

16
Contribution of Interstitial-Assisted Mechanism

• According to theory, for diffusion via the
  vacancy mechanism, the activation energy for
  impurity diffusion should be smaller than that
  for self-diffusion
• Experiments show for Boron in Ge
• An interstitial-assisted mechanism may need to be
  considered

Hu. Phys. Status Solidi B 60, 595
(1973). Uppal et al. JAP 96, 1376,
(2004). Fuchs et al. Phy. Rev. B. 51, 16817
(1995).
17
MBE-grown Boron Doped Multilayer Structure
B-doped layers
Ge Substrate

• B-doped multilayer structure is used to study
  equilibrium and non-equilibrium transient effects
  of B diffusion in Ge
• Alternating layers of 100 nm Ge spacer and 10 nm
  B-doped layer
• Grown by Dr. Stefan Ahlers and Prof. G.
  Abstreiter at the Walter-Schottky Institut, Munich

18
Preliminary SIMS Results

• Samples were annealed at 900C for 18 min
• Sample with Ge implantation shows slightly
  enhanced diffusion
• However, effects of implantation damage are still
  inconclusive from the preliminary results

19
Future Milestones

• Year 4 Milestone
• Self-diffusion in strained and relaxed
  isotopically enriched SiGe layers

• By varying x and y, compressive and tensile
  strains can be introduced
• This structure will be used to study effect of
  strain on Si and Ge self-diffusion in SiGe

20
Fabrication and characterization of GeOI

• GSR Eric Liu
• Faculty PI Prof. Nathan Cheung
• Department of EECS
• UC-Berkeley

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Motivations

• Ultra-short channel ballistic transport initial
  velocity (low field mobility) is important
• Advantageous for low supply voltage

22

• 2005 milestones
• Increase thermal robustness of GeOI
• Use of pseudo-MOSFET structure to evaluate
  transferred layer electronic properties
• 2006 milestones
• Prototype GeOI MOSFET performance evaluation
• Demonstrate GeSiOI layer transfer using GeSi
• epi wafers
• Investigate interfacial quality with high-k
  dielectric as buried insulator
• Achievements
• GeOI shows good thermal robustness at 550oC
• Model analysis of GeOI pseudo-MOSFET
• Forming gas annealing reduces fixed interface
  charges Qf but generates interface traps Qit

23
2005-2006 Accomplishments
Pseudo MOSFET Characterization
The bonding interface charge lt Qf 1011/cm2,
positive
Eric Liu, UCB
24
GeOI after 550oC, 1 hr annealing

• GeOI shows good thermal robustness

25
Chemical-Mechanical-Polishing Set-up
CMP Set-Up Lapping machine
Pad (SBT Company) Polishing cloth Rayon-Fine 8
Diameter PSA P/N PRF08A-10 Slurry 0.2µm SiO2
particle mixed with KOH
26
GeOI surface smoothing with CMP

• GeOI surface can be smoothed down to RMS 0.3nm
• by CMP
• GeOI substrates are ready for device fabrication

27
Pseudo-MOSFET 4-probe-configuration
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Forming gas annealing effects

• Forming gas improves
• hole accumulation at
• Ge/SiO2 interface
• Forming gas reduces electron inversion at Ge/SiO2
  interface

29
Interface traps (Qit) behavior of forming gas
anneal

• Forming gas decreases Qit, 0 to 5x1011/cm2

30
2006 Goals

• Qit reduction with surface encapsulation and
• optimized Temperature-Time cycles
• GeOI using Epi Ge wafer as donor wafer
• (with Yihwan Kim , AMAT)
• Prototype GeOI MOSFET with high-K dielectric
• and evaluation