Chapter 10 - Part 1 - PPT - Mano

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(No Transcript)
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10-1

• Computer Specification
• Instruction Set Architecture (ISA) - the
  specification of a computer's appearance to a
  programmer at its lowest level
• Computer Architecture - a high-level description
  of the hardware implementing the computer derived
  from the ISA
• The architecture usually includes additional
  specifications such as speed, cost, and
  reliability.

3
Introduction (continued)

• Simple computer architecture decomposed into
• Datapath for performing operations
• Control unit for controlling datapath operations
• A datapath is specified by
• A set of registers
• The microoperations performed on the data stored
  in the registers
• A control interface

4
Datapaths10-2

• Guiding principles for basic datapaths
• The set of registers
• Collection of individual registers
• A set of registers with common access resources
  called a register file
• A combination of the above
• Microoperation implementation
• One or more shared resources for implementing
  microoperations
• Buses - shared transfer paths
• Arithmetic-Logic Unit (ALU) - shared resource
  for implementing arithmetic and logic
  microoperations
• Shifter - shared resource for implementing shift
  microoperations

5
Datapath ExampleFigure 10-1

• Four parallel-loadregisters (R0-R3)
• Two mux-based register selectors
• Register destination decoder
• Mux B for external constant input
• Buses A and B with externaladdress and data
  outputs
• ALU and Shifter withMux F for output select
• Mux D for external data input
• Logic for generating status bitsV, C, N, Z

Load enable
A select
B select
Write
A address
B address
n
D data
Load
R0
2
2
n
n
Load
R1
0
n
1
MUX
2
n
3
0
1
MUX
Load
2
R2
3
n
n
Load
R3
n
n
0
1
2
3
n
Register file
Decoder
A data
B data
D address
n
n
2
Constant in
Destination select
n
1
0
MB select
MUX B
Address
n
Bus A
Out
n
Bus B
Data
A
B
Out
n
G select
H select
B
A
B
4
2
S
S
C
20
in
I
I
V
Shifter
0
0
Arithmetic/logic
L
R
unit (ALU)
C
H
G
N
n
n
Z
Zero Detect
0
1
MF select
Function unit
MUX F
F
Data In
n
n
0
1
MD select
MUX D
Bus D
n
6
Datapath Example Performing a Microoperation

• Microoperation R0 ? R1 R2

• Apply 10 to B select to place contents of R2
  onto B data and apply 0 to MB select to place B
  data on Bus B

7
Arithmetic Logic Unit (ALU)

• In this and the next section, we deal with
  detailed design of typical ALUs and shifters
• Decompose the ALU into
• An arithmetic circuit
• A logic circuit
• A selector to pick between the two circuits
• Arithmetic circuit design
• Decompose the arithmetic circuit into
• An n-bit parallel adder
• A block of logic that selects four choices for
  the B input to the adder
• See next slide for diagram

8
Arithmetic Circuit DesignFigure 10-3 and Table
10-1 and table 10-2 (pages 435, 438)

• There are only four functions of B to select as Y
  in G A Y
• All 0s
• B
• B
• All 1s

Cin 0
Cin 1
G A
G A 1
G A B
G A B 1
Subtraction
G A 1
G A
C
in
n
A
X
n-bit
n
n
G X Y Cin
parallel
B
adder
n
B input
Y
logic
S
0
S
1
C
out
9
Logic Circuit

• The text gives a circuit implemented using a
  multiplexer plus gates implementing AND, OR, XOR
  and NOT
• Here we custom design a circuit for bit Gi by
  beginning with a truth table organized as logic
  operation K-map and assigning (S1, S0) codes to
  AND, OR, etc.
• Gi S0 Ai Bi S1 Ai Bi S0 Ai Bi
  S1 S0 Ai
• Gate input count forMUX solution gt 29
• Gate input count forabove circuit lt 20
• Custom design better

S1S0 AND OR XOR NOT
AiBi 0 0 0 1 1 1 1 0
0 0 0 0 0 1
0 1 0 1 1 1
1 1 1 1 0 0
1 0 0 1 1 0
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Arithmetic Logic Unit (ALU)

• The custom circuit has interchanged the (S1,S0)
  codes for XOR and NOT compared to the MUX
  circuit. To preserve compatibility with the text,
  we use the MUX solution.
• Next, use the arithmetic circuit, the logic
  circuit, and a 2-way multiplexer to form the ALU.
  See the next slide for the bit slice diagram.
• The input connections to the arithmetic circuit
  and logic circuit have been been assigned to
  prepare for seamless addition of the shifter,
  keeping the selection codes for the combined ALU
  and the shifter at 4 bits
• Carry-in Ci and Carry-out Ci1 go between bits
• Ai and Bi are connected to both units
• A new signal S2 performs the arithmetic/logic
  selection
• The select signal entering the LSB of the
  arithmetic circuit, Cin, is connected to the
  least significant selection input for the logic
  circuit, S0.

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Arithmetic Logic Unit (ALU)Figure 10-7

• The next most significant select signals, S0 for
  the arithmetic circuit and S1 for the logic
  circuit, are wired together, completing the two
  select signals for the logic circuit.
• The remaining S1 completes the three select
  signals for the arithmetic circuit.

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Combinational Shifter Parameters10-4

• Direction Left, Right
• Number of positions with examples
• Single bit
• 1 position
• 0 and 1 positions
• Multiple bit
• 1 to n 1 positions
• 0 to n 1 positions
• Filling of vacant positions
• Many options depending on instruction set
• Here, will provide input lines or zero fill

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4-Bit Basic Left/Right Shifter (Figure 10-8)

• Serial Inputs
• IR for right shift
• IL for left shift
• Serial Outputs
• R for right shift (Same as MSB input)
• L for left shift (Same as LSB input)

• Shift Functions(S1, S0) 00 Pass B unchanged
  01 Right shift
  10 Left shift 11 Unused

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Barrel Shifter(Figure 10-9)

• A rotate is a shift in which the bits shifted out
  are inserted into the positions vacated
• The circuit rotates its contents left from 0 to 3
  positions depending on SS 00 position
  unchanged S 10 rotate left by
  2 positionsS 01 rotate left by 1 positions
  S 11 rotate left by 3 positions
• See Table 10-3 in text for details (page 440)

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Barrel Shifter (continued)

• Large barrel shifters can be constructed by
  using
• Layers of multiplexers - Example 64-bit
• Layer 1 shifts by 0, 16, 32, 48
• Layer 2 shifts by 0, 4, 8, 12
• Layer 3 shifts by 0, 1, 2, 3
• See example in section 12-2 of the text
• 2 dimensional array circuits designed at the
  electronic level

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Datapath Representation10-5

• Here we move up one level in the hierarchy from
  that datapath
• The registers, and the multiplexer, decoder, and
  enable hardware for accessing them become a
  register file
• A register file is an array of fast registers
• The ALU, shifter, Mux F and status hardware
  become a function unit
• The remaining muxes and buses which handle data
  transfers are at the new level of the hierarchy

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Datapath Representation (continued)

• In the register file
• Multiplexer select inputs become A address and B
  address
• Decoder input becomes D address
• Multiplexer outputs become A data and B data
• Input data to the registers becomes D data
• Load enable becomes write
• The register file now appears like a memory based
  on clocked flip-flops (the clock is not shown)
• The function unit labeling is quite
  straightforward except for FS

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Definition of Function Unit Select (FS)
Codes(Table 10-4, page 443))
G
Select,
H
Select,
and
MF
in T
of
FS
Codes

• Boolean
• Equations
• MF F3 F2
• Gi Fi
• Hi Fi

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The Control Word

• The datapath has many control inputs
• The signals driving these inputs can be defined
  and organized into a control word
• To execute a microinstruction, we apply control
  word values for a clock cycle. For most
  microoperations, the positive edge of the clock
  cycle is needed to perform the register load
• The datapath control word format and the field
  definitions are shown on the next slide

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The Control Word Fields

• Fields
• DA D Address (destination)
• AA A Address
• BA B Address (source for MUXB
• MB Mux B (constant/source
• FS Function Select
• MD Mux D
• RW Register Write
• The connections to datapath are shown in the next
  slide

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Control Word Block Diagram (Figure 10-11)
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Control Word EncodingTable 10-5
Encoding of Control
W
D
A
,
AA,
B
A
MB
FS
MD
R
W
Function
Code
Function
Code
Function
Code
Function
Code
Function
Code

R
0
000
Register
0
0000
Function
0
No write
0
F
A
R
1
001
Constant
1
0001
Data In
1
Write
1

F A
1

R
2
010
0010


F A
B



R
3
011
0011
F A
B
1


R
4
100
0100
F A
B


R
5
101
0101

F A
B
1
-

R
6
110
0110
F A
1

R
7
111
0111
F A
Ù

1000
F A
B
Ú

1001
F A
B
1010

Å
F A
B
1011
F

A
1100

F B
1101

F
sr
B
1110

F
sl
B
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Microoperations for the Datapath - Symbolic
RepresentationTable 10-6
Micr
o-
op
eratio
n
D
A
A
A
B
A
M
B
F
S
M
D
R
W

R
1
R
2
R
3
R
e
g
ister
F
unction
Write
R
1
R
2
R
3

F A
B
1



R
4

R
6
R
e
g
ister
F
unction
Write
R
4
s
l R6
F
sl
B


R
7
R
7

Re
gister
Function
Write
R
7
R
7 1

F A
1



R
1
R
0

Con
s
tant
Func
tio
n
Write
R
1
R
0 2

F A
B




R
3
R
eg
i
s
t
e
r


N
o Wr
it
e
Data out
R
3

R
4



Data in
Write
R
4
D
ata in

Å
R
5
R
0
R
0
R
e
g
ister
F
unction
Write
R
5 0
F A
B

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Microoperations for the Datapath - Binary
RepresentationTable 10-7
m
Microoperations from T
a
Binary C
o
o

• Results of simulation of the above on the next
  slide

25
Datapath SimulationFigure 10-12
26
Instruction Set Architecture (ISA) for Simple
Computer (SC)10-7

• A programmable system uses a sequence of
  instructions to control its operation
• An typical instruction specifies
• Operation to be performed
• Operands to use, and
• Where to place the result, or
• Which instruction to execute next
• Instructions are stored in RAM or ROM as a
  program
• The addresses for instructions in a computer are
  provided by a program counter (PC) that can
• Count up
• Load a new address based on an instruction and,
  optionally, status information

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Instruction Set Architecture (ISA) (continued)

• The PC and associated control logic are part of
  the Control Unit
• Executing an instruction - activating the
  necessary sequence of operations specified by the
  instruction
• Execution is controlled by the control unit and
  performed
• In the datapath
• In the control unit
• In external hardware such as memory or
  input/output

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ISA Storage ResourcesFigure 10-13

• The storage resources are "visible" to the
  programmer at the lowest software level
  (typically, machine or assembly language)
• Storage resourcesfor the SC gt
• Separate instruction anddata memories
  imply"Harvard architecture"
• Done to permit use ofsingle clock cycle
  perinstruction implementation
• Due to use of "cache" in modern
  computerarchitectures, is a fairlyrealistic
  model

Program counter
(PC)
Instruction
memory
15
x
2
16
Register file
x
8
16
Data
memory
15
x
2
16
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ISA Instruction Format

• A instruction consists of a bit vector
• The fields of an instruction are subvectors
  representing specific functions and having
  specific binary codes defined
• The format of an instruction defines the
  subvectors and their function
• An ISA usually contains multiple formats
• The SC ISA contains the three formats presented
  on the next slide

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ISA Instruction FormatFigure 10-14

• The three formats are Register, Immediate, and
  Jump and Branch
• All formats contain an Opcode field in bits 9
  through 15.
• The Opcode specifies the operation to be
  performed
• More details on each format are provided on the
  next three slides

31
ISA Instruction Format (continued)

• This format supports instructions represented by
• R1 ? R2 R3
• R1 ? sl R2
• There are three 3-bit register fields
• DR - specifies destination register (R1 in the
  examples)
• SA - specifies the A source register (R2 in the
  first example)
• SB - specifies the B source register (R3 in the
  first example and R2 in the second example)

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ISA Instruction Format (continued)

• This format supports instructions described by
• R1 ? R2 3
• The B Source Register field is replaced by an
  Operand field OP which specifies a constant.
• The Operand
• 3-bit constant
• Values from 0 to 7
• The constant
• Zero-fill (on the left of) the Operand to form
  16-bit constant
• 16-bit representation for values 0 through 7

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ISA Instruction Format (continued)

• This instruction supports changes in the sequence
  of instruction execution by adding an extended,
  6-bit, signed 2s-complement address offset to the
  PC value
• The 6-bit Address (AD) field replaces the DR and
  SB fields
• Example Suppose that a jump is specified by the
  Opcode and the PC contains 45 (00101101) and
  Address contains 12 (110100). Then the new PC
  value will be00101101 (1110100) 00100001
  (45 ( 12) 33)
• The SA field is retained to permit jumps and
  branches on N or Z based on the contents of
  Source register A

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ISA Instruction Specifications

• The specifications provide
• The name of the instruction
• The instruction's opcode
• A shorthand name for the opcode called a mnemonic
• A specification for the instruction format
• A register transfer description of the
  instruction, and
• A listing of the status bits that are meaningful
  during an instruction's execution (not used in
  the architectures defined in this chapter)

35
ISA Instruction Specifications (continued)
36
ISA Instruction Specifications (continued)
37
ISAExample Instructions and Data in Memory
38
Single-Cycle Hardwired Control10-8

• Based on the ISA defined, design a computer
  architecture to support the ISA
• The architecture is to fetch and execute each
  instruction in a single clock cycle
• The datapath from Figure 10-11 will be used
• The control unit will be defined as a part of the
  design
• The block diagram is shown on the next slide

39
IR(86) IR(20)
Extend
V
C
Branch
PC
N
Control
Z
Address
J
P
B
B
L
C
Instruction
RW
memory
D
Register
DA
Instruction
file
AA
BA
A
B
Zero fill
IR(20)
Constant
in
Instruction decoder
1
0
MB
MUX B
Address out
Bus A
Bus B
Data out
MW
D
B
A
F
M
R
M
M
J
P
B
A
A
A
S
D
W
W
B
B
L
C
A
B
Data in
Address
FS
CONTROL
V
Data
Function
C
memory
unit
Figure 10-15
N
Data out
Z
F
Data in
0
1
MD
MUX D
Bus D
DATAPATH
40
The Control Unit

• The Data Memory has been attached to the Address
  Out and Data Out and Data In lines of the
  Datapath.
• The MW input to the Data Memory is the Memory
  Write signal from the Control Unit.
• For convenience, the Instruction Memory, which is
  not usually a part of the Control Unit is shown
  within it.
• The Instruction Memory address input is provided
  by the PC and its instruction output feeds the
  Instruction Decoder.
• Zero-filled IR(20) becomes Constant In
• Extended IR(86) IR(20) and Bus A are address
  inputs to the PC.
• The PC is controlled by Branch Control logic

41
PC Function (continued)

• Branch Control determines the PC transfers based
  on five of its inputs defined as follows
• N,Z negative and zero status bits
• PL load enable for the PC
• JB Jump/Branch select If JB 1, Jump, else
  Branch
• BC Branch Condition select If BC 1, branch
  for N 1, else branch for Z 1.
• The above is summarize by the following table

PC Operation PL JB BC
Count Up 0 X X
Jump 1 1 X
Branch on Negative (else Count Up) 1 0 1
Branch on Zero (else Count Up) 1 0 0
42
Instruction Decoder

• The combinational instruction decoder converts
  the instruction into the signals necessary to
  control all parts of the computer during the
  single cycle execution
• The input is the 16-bit Instruction
• The outputs are control signals
• Register file addresses DA, AA, and BA,
• Function Unit Select FS
• Multiplexer Select Controls MB and MD,
• Register file and Data Memory Write Controls RW
  and MW, and
• PC Controls PL, JB, and BC
• The register file outputs are simply pass-through
  signals DA DR, AA SA, and BA
  SBDetermination of the remaining signals is more
  complex.

43
Instruction Decoder (continued)

• The remaining control signals do not depend on
  the addresses, so must be a function of IR(139)
• Formulation requires examining relationships
  between the outputs and the opcodes
• Observe that for other than branches and jumps,
  FS IR(129)
• This implies that the other control signals
  should depend as much as possible on IR(1513)
  (which actually were assigned with decoding in
  mind!)
• To make some sense of this, we divide
  instructions into types as shown in the table on
  the next page

44
Instruction Decoder (continued)
45
Instruction Decoder (continued)

• The types are based on the blocks controlled and
  the seven signals to be generated types can be
  divided into two groups
• Datapath and Memory Control (First 4 types)
• PC Control (Last 3 types)
• In Datapath and Memory Control blocks controlled
  are considered
• Mux B (1st and 4th types)
• Memory and Mux D (2nd and 3rd types)
• By assigning codes with no or only one 1 for
  these, implementation of MB, MD, RW and MW are
  simplified.
• In Control Unit more of a bit setting approach
  was used
• Bit 15 Bit 14 1 were assigned to generate PL
• Bit 13 values were assigned to generate JB.
• Bit 9 was use as BC which contradicts FS 0000
  needed for branches. To force FS(6) to 0 for
  branches, Bit 9 into FS(6) is disabled by PL.
• Also, useful bit correlations between values in
  the two groups were exploited in assigning the
  codes.

46
Instruction Decoder (continued)

• The end result by use of the types, careful
  assignment of codes, and use of don't cares,
  yields very simple logic
• This completes thedesign of most of the
  essential parts ofthe single-cycle simple
  computer