Pseudo-Random Testing of Arithmetic Circuits

1
Pseudo-Random Testing of Arithmetic Circuits

• Presenter Canturk ISCI
• Supervisors Dr. R.C.S. Morling
• Prof. I. Kale

2
Project Goals
What we want to do

• Generate parameterized signed parallel multiplier
  in VHDL
• Investigate pattern generation techniques with
  direct output sampling
• Deterministic exhaustive/nonexhaustive
• Pseudorandom exhaustive/nonexhaustive
• CA vs. LFSR
• Repetitive patterns
• Output compression signature analysis
• Compare with direct measurement

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Project Goals
What we want to do

• Extend to MAC structures, include
  nonlinearities ? Rounders, for precision
• ? Limiters, for overflow
• Alternative multiplier types
• CPA, CSA, Booths or Wallace

Summing up into...

• To investigate BIST techniques for multiplier
  based arithmetic processors and extension of the
  techniques for efficient testing of circuits with
  nonlinearities.

4
Project Methodology
How well do it

• Build Background (Inevitably)
• Testing, BIST, PRBS Generation and output
  compression techniques
• Literature Survey
• Papers on multiplier testing
• Previous work on testing MAC structures -
  nonlinearities
• Describe experimental route
• Initiation Part-I and II ? for 3x3 CPA
  multiplier
• Design parameterized multiplier
• VHDL ? MGCs Renoir
• Investigate BIST schemes for multiplier
• Fault simulation ? MGCs QuickfaultII
• Apply output compression ?
• Back to design phase for complete BIST circuit
• Extend to MAC
• Alternative multipliers

5
Project Motive
Why we want to do it

• DSPs and GPPs ? Multipliers are critical
  functional blocks of datapath architectures
• low controllability and observability ? BIST
• A thorough investigation of BIST for parallel
  signed multipliers with modified MSB
• BIST methods for MAC structures with
  nonlinearities
• No profound research in literature

For Quoted Research/ More Info

• See report section X - References Bibliography

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Anticipated Hindrances
Expected causes of delay in project progress

• Design in VHDL, fault simulation schematic based,
  Renoir QuickFault not compatible
• Synthesis with Autologic as stop-over
• Design Architect for symbol readability
• Deterministic fault simulation
• Accurate, but high computation cost
• Each BIST alternative ? separate design
• Use Matlab scripts to emulate circuits,
• Generate stimuli in Software ? dofiles

AND ABOVE ALL
TIME! ?
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BIST Theory
1) LFSR

• Shift register, XOR ( mod2 add) feedback of
  selected flip-flop outputs (taps)
• Taps chosen properly ? M-Sequence all 2n-1
  states
• 1 Forbidden state (Not necessarily 000) or
  DeBrujn Counter

G(x) a0x0 a1x1 a2x2 amxm ?writing G(x)
for yi Gy(x) y0x0 y1x1 y2x2 ymxm
.. ?Substitute above yi relation
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BIST Theory
2) CA

• Similar to LFSR, BUT?
• No global feedback (good for VLSI)
• Always an XOR feedback to cells (more hardware)
• Theory of 90 and 150 cells - proper combination
  produces M-Sequence

T-matrix ?
In General?
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BIST Theory
3) Signature Analyzer

• Same as LFSR serial data XORed into LFSRs
  feedback input
• Only for a single output data ? MISR

? Input 1010011 ? I(x)x6 x4 x1 1
3) MISR
Si1(x) Ii(x) x.Si(x) mod D(x)
Fault Masking Probability
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Design Flow
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Design Entry
1) Signed Parallel CPA Multiplier

• Matrix like structure
• FA Function
• Sum A(B)(Cin) (A)B(Cin) (A)(B)Cin
  ABCin
• A ? B ? Cin
• Cout AB ACin BCin
• MSBFA Function
• Sum Same function
• Cout SN AN-1BN-1 AN-1(CN-1) BN-1(CN-1)
• Parameterized Renoir Implementation ? Appendix
  B-2
• Uses bitproduct and carry matrices and 2D sum
  array

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Design Entry
2) Signature Analyzer

• Parameterized (VHDL in Appendix A-8)
• Width ? width of signature analyzer
• Polynomial ? characteristic polynomial, width1
  bits as poly(width).xwidthpoly(width-1).
  xwidth-1 poly(1). x1 poly(0). x0
• Scan Input disables parallel inputs when high

3) LFSR

• Parameterized (VHDL in Appendix A-10)
• Width ? width of LFSR
• Seed ? Initial seed
• Taps ? Tap locations

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Design Entry
4) TOP Level circuit (LFSRMultSignNxN)

• Almost Completely Parameterized (Renoir Design ?
  Appendix B-4)
• Can parameterize Multiplier size, LFSR length,
  seed, taps and signature analyzer characteristic
  polynomial
• Utilizes Repetitive Patterns in BIST ? Coming in
  Slide 19
• Multipliers AB Input assignments need to be
  done manually as they depend on chosen repetition
  length

5) Larger Circuits

• Very easy to generate (Appendices B-5..7), only
  define a few parameters ?
• Multiplier size, LFSR length, seed determined
  tap locations for M-sequence,
• signature analyzer characteristic polynomial
• we want as many taps as possible for least fault
  masking!

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BIST Techniques
THE CORE OF PROJECT
Preludes

• All design blocks synthesized into schematic
• Examples are in slides 15, 22, 23
• Information about Fault simulation and Modeling
• Fault types
• Single stuck at model
• CFM ? good but CFC mediocre for fault coverage
• Fault simulation techniques
• Software Simulation techniques
• Deterministic vs. Statistical simulators
• Fault simulation techniques
• Hierarchical vs. Board level faulting ?

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BIST for 8x8 Multiplier Board level faulting
Board Level Faulting

• Greens are s_at_1
• Reds are s_at_0
• 932 faults total

• Prior symbol editing makes design readable
• Same schematic until addition of BIST circuit

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BIST for 8x8 Multiplier Board level faulting
16 bit Upcounter

• First full exhaustive test
• 100 fault coverage is achieved in 32897 cycles
  out of 64K
• 32000 vectors for just 932 faults ?
• Vast redundancy ? indicators
• Large No Detection regions in histogram
• Flat regions in fault coverage plot

16 bit Downcounter

• Full exhaustive test
• 100 fault coverage is achieved in again 32897
  cycles out of 64K
• Again huge redundancy!!

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BIST for 8x8 Multiplier Board level faulting
16 bit Rolling 0

• The bitproducts suggest as a promising test
• 98.07 fault coverage, with only these 16 vectors
  
• Addition of all 0s prompted by HLandH gates
• 100 fault coverage with just 17 vectors
• Seems like we found a prominent BIST for
  multiplier!
• BUT!gtgt

HLandH
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BIST for 8x8 Multiplier Hierarchical faulting
Hierarchical Faulting

• Controversy is how to choose the primitive levels
• No standard ? each vendor supplies different
  primitives
• Go to the other extreme AND-OR-INV level ? most
  pessimistic case
• See report figures VI-19 VI-24 for complete
  story
• Now 6008 faults total

16 bit Rolling 0 - AGAIN

• Fault coverage drops to a measly 81.6
• Makeshift modifications do not help significantly

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BIST for 8x8 Multiplier Hierarchical faulting
16 bit Downcounter Again!

• Will use as a benchmark to the extent of
  achievable fault coverage
• Fault coverage 98.49 after all possible patterns
  applied
• Interesting observation ? Most of undetected
  faults in MSB adders

Repetitive patterns Upcounter k4

• 3,5,23 suggest excellent fault coverage
  with repetitive patterns
• 97.02 fault coverage with 228 lt 28 patterns
• Looks very promising and is so

PRBS techniques LFSR CA

• 13 different BIST techniques investigated, with
  different lengths, various methodologically
  determined seeds, making use of repetitive
  patterns

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BIST for 8x8 Multiplier Hierarchical faulting
LFSR CA - Story in a nutshell

• In general repetitive patterns found to be very
  efficient
• CA insignificantly better than LFSRs
• Below table summarizes all?

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BIST for 8x8 Multiplier Hierarchical faulting
Final Technique 8 bit LFSR, seedx7B

• There is no ultimately better technique,
  decisions can be disputed
• Depends on target fault coverage
• 8 bit LFSR, using repetition length4, seedx7B
  is final decision

How we determine seed x7B as a probably efficient
initial seed for LFSR From the histogram for 8
bit LFSR with seed x01
Fault coverage for 8 bit LFSR, seedx7B
Corresponds to seed x7B
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BIST for 8x8 Multiplier Including BIST
circuitry
Generated Signature analyzer
Output compression 16 bit MISR

• We use a high weight polynomial for MISR ?
• Reduce fault masking
• Only 28 vectors possible
• Multiplier structure ? expect low fault masking
• 96.80 fault coverage with only 111 vectors
• (except for 1 fault / 6008)

Input pattern generation 8bit LFSR, seedx7B

• 8 bit LFSR with seed x7B already decided
• Generated schematic in next slide
• ltUsing repetition length 4gt
• 97.07 fault coverage with lt 256 vectors

Complete Top level Design
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BIST for 8x8 Multiplier Including BIST
circuitry
Generated 8 bit LFSR

• Fault coverage curve for the top level
  circuit-with only multiplier faulted ?

• Fault coverage curve saturates with first 132
  patterns

Faulting BIST circuitry in fault simulation

• Total faults increase to 8016
• Fault coverage 96.95
• Very close to only multiplier case

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BIST for Larger Multipliers With Repetitive
patterns

• Could only simulate 16x16
• Faults increased to 26456 x4 of 8x8 multiplier
• Using 8 bit LFSR with repetition length 4
• 4x4 repeated patterns for both a b inputs
• Total only 256 patterns as in 8x8 multiplier
  case

• 97 fault coverage in only 57 cycles
• Climbs up to 98.83 in the whole 256 cycles
• Even better than 8x8 multiplier,
• with no additional input patterns

32x32 24x24 Multipliers

• 32x32 Multiplier ? 111128 faults
• Synthesis OK, Fault simulation ?
• Requires more memory
• Or statistical simulation ? QuickGrade, but then
  results are not comparable

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Conclusions

• Board level faulting is too abstract
• Exhaustive testing under Hierarchical Faulting
  Does not guarantee 100 fault coverage ? Logic
  redundancies in unoptimized logic
• Exhaustive testing under Hierarchical Faulting
  Does not guarantee 100 fault coverage
• Most faults residing in MSBFA may suggest an
  inherent redundancy in modified signed addition
• Described seed determination method is seen to be
  effective
• Insignificant improvement with CA w.r.t. LFSR
• Repetitive patterns extremely successful
• High weight signature analysis has very low fault
  masking behavior with parallel signed multiplier
• Repetitive patterns provide efficient testing
  with constant set of test vectors independent of
  multiplier size

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Future Work

• investigation of BIST techniques for MAC ?
  Nonlinearities
• Determination of the most compact deterministic
  test (26)
• Investigation of other multipliers ? Results
  already anticipated (3)
• Standardization of fault modeling with CFM (23,
  24)
• Improving CFC for reliable measures
• More computation power ? Larger multipliers
  should be verified

END of PRESENTATION
Thanks for Listening