??????? ??? ?? VHDL? ??? ??

1
??????? ??? ?? VHDL? ??? ??
2002???????????

• "? ??? 2002?? ????????? ???? ??? ??? ??
  (KRF-2002-048-D00058)"
• " This work was supported by Korea Research
  Foundation Grant. (KRF-2002-048-D00058)"

2
?1? ??????
? 7? ??????? ??

• 1. ????? ??
• ?? 7.1 ????? ??
• 2. ??????? ??
• ?? 7.2 ??????

3
?1? ??????
? 7? ??????? ??

• ltVHDL ??gt
• 1  p1 process(a, b)         -- ????? process?(??
  ??? a, b)
• 2      begin                               
• 3          out1  lt a and b  -- ??? ??? ???,
  ?? ?? out1? ??
• 4    end process p1         -- flip_flop?
  ??   
• 5  p2 process( clk )         -- ???? process,
  ???? clk
• 6       begin
• 7       if(clk'event and clk'1') then --
  clk? rising edge??? ?? ?? ??? ??
• 8         out2  lt a and b    --
  flip_flop? ??
• 9       end if                      
• 10     end process p2

4
?2? ??(latch) ??? ??
? 7? ??????? ??

• 1. ????? ???
• ?? 7.3 D_latch (a) ?? (b) ???  (c) ??? ??

5
?2? ??(latch) ??? ??
? 7? ??????? ??

• 2. ????(procedure)? ??? ????
• ltVHDL ??gt
•       library IEEE
•       use IEEE.std_logic_1164.all
•       entity procedure_latch is
•         port (clk in std_logic
•            a, b in std_logic_vector(1 downto
  0)
•            y out std_logic_vector(1 downto 0))
  
•       end procedure_latch
•       architecture latch_example of
  procedure_latch is
• 1       procedure latch(clk, a, b in std_logic
  
• 2                      signal z_out out
  std_logic) is
• 3         begin
• 4           if clk '1' then
• 5             z_out lt a and b
• 6           end if
• 7       end latch
• 8      begin

?? 7.4 latch? ????
6
?2? ??(latch) ??? ??
? 7? ??????? ??

• 3. ?? ? ?? ??(simple and multiple latch)
• ltVHDL ??gt
•     library IEEE
•     use IEEE.STD_LOGIC_1164.all,
  IEEE.NUMERIC_STD.all
•     entity LATCH_EX is
•       port (en1, en2, en3, a1, a2, b2, c2, a3,
  b3, c3 in std_logic
•             y1, y2, y3 out std_logic)
•     end LATCH_EX
•     architecture LATCH_example of LATCH_EX is
•   1      signal M2 std_logic
•        begin
•   2   P1 process (en1, en2, en3, a1, a2, b2, c2,
  a3, b3, c3)
•   3          variable M3 std_logic
•   4       begin
•   5         if (en1 '1') then
•   6            z_out1 lt 'a1'
•   7         end if
•   8         if (en2 '1') then
•   9           M2 lt a2 nand b2       (a)

?? 7.5 ??? ????
7
?2? ??(latch) ??? ??
? 7? ??????? ??

• 4. Perset/Clear ??? ??
• ltVHDL ??gt
•     library IEEE
•     use IEEE.std_logic_1164.all,
  IEEE.numeric_std.all
•     entity PRCL_example is
•       port (en1, clear1, a1, en2, clear2, a2,
  en3, preset3, a3, en4, preset4, a4
•             en5, preset5, clear5, a5 in
  std_logic
•             y1, y2, y3, y4, y5 out std_logic)
•     end PRCL_example
•     architecture LATCH_example of PRCL_example is
  
•        begin
•   1     process (en1, clear1, a1, en2, clear2,
  a2, en3, preset3, a3, en4, preset4, a4
•                  en5, preset5, clear5, a5)
•   2       begin
•   3         if (clear1 '0') then
•   4            z_out1 lt '0'
•   5          elsif (en1 '1') then
•   6             z_out1 lt a1
•   7         end if                      

8
?2? ??(latch) ??? ??
? 7? ??????? ??

• 12         end if                       
  
• 13         if (preset3 '0') then            
• 14             z_out3 lt '1'
• 15           elsif (en3 '1') then
• 16             z_out3 lt a3
  
• 17         end if                       
• 18           if (preset4 '1') then            
• 19             z_out4 lt '1'        
• 20           elsif (en4 '1') then
                    
• 21              z_out4 lt a4               
• 22           end if
• 23           if (clear5 '1') then            
• 24              z_out5 lt '0'        
  
• 25           elsif (preset5 '1') then       
• 26              z_out5 lt '1'
• 27           elsif (en5 '1') then
• 28              z_out5 lt a5               
  
• 29           end if
• 30       end process                     

?? 7.6 Preset/Clear ??? ????
9
?2? ??(latch) ??? ??
? 7? ??????? ??

• 5. ?? enable ??? ??
• lt VHDL ??gt
•     library IEEE
•     use IEEE.std_logic_1164.all
•     entity multienable_LATCH is
•        port (en1, en2, en3, A1, A2, A3 in
  std_logic
•             Y out std_logic)
•     end multienable_LATCH
•     architecture LATCH_example of
  multienable_LATCH is 
•       begin
• 1       process (en1, en2, en3, a1, a2, a3)
• 2        begin
• 3         if (en1 '1') then
• 4           z_out lt a1
• 5         elsif (en2 '1') then
• 6           z_out lt a2
• 7         elsif (en3 '1') then
• 8           z_out lt a3

?? 7.7 ?? enable??? Latch????
10
?3? Flip Flop? ??
? 7? ??????? ??

• 1. Flip_Flop? ??
• (a) ??         (b) ???              (c)
  clk? ?? ???? ??              
• ?? 7.8 Edge trigger D Flip_Flop 

11
?3? Flip Flop? ??
? 7? ??????? ??

• 2. D Flip_Flop
• ?? 7.9 D Flip_Flop? MUX????
• ltVHDL??gt
• 1    process (clk)
• 2      begin
• 3       if (clk'event and clk'1') then    --
  clk? ?? ????
• 4           q lt d                   
  -- d??? q? ??
• 5           end if
• 6    end process

12
?3? Flip Flop? ??
? 7? ??????? ??

• 2. if?? ??? ??? Flip_Flop ??
• ltVHDL ??gt
•     library IEEE
•     use IEEE.std_logic_1164.all
•     entity FlipFlop_EX1 is
•        port (clk, a, b in std_logic
•             z_out out std_logic)
•     end FlipFlop_EX1
•     architecture FlipFlop_example of FlipFlop_EX1
  is 
•       begin
• 1      process (clk)
• 2        begin
• 3         if clk'event and clk '1') then
• 4           z_out lt a and b
• 5         end if
• 6      end process                          
•     end FlipFlop_example

?? 7.10 Flip_Flop? ????
13
?3? Flip Flop? ??
? 7? ??????? ??

• 3. if?? ??? ? ?? Flip_Flop ??
• ltVHDL ??gt
•      library IEEE
•      use IEEE.std_logic_1164.all
  IEEE.numeric_std.all
•      entity FlipFlop_EX2 is
•         port (clk, a, b, c, d, e in std_logic
•              z_out out std_logic)
•      end FlipFlop_EX2
•      architecture combi_FlipFlop of FlipFlop_EX2
  is 
• 1         signal M std_logic  
• 2      begin
• 3      process (clk)
• 4         variable N std_logic
• 5        begin
• 6         if rising_edge(clk) then
• 7            M lt (a nand b)
• 8            N (c or d)
• 9            z_out lt  not (M or N or e)

?? 7.11 Flip_Flop? ????
14
?3? Flip Flop? ??
? 7? ??????? ??

• 4. wait until?? ??? Flip_Flop ??
• ltVHDL ??gt
•      library IEEE
•      use IEEE.std_logic_1164.all
•      entity FlipFlop_EX3 is
•         port (clk, a, b in std_logic
•              z_out out std_logic)
•      end FlipFlop_EX3
•      architecture FlipFlop_example of
  FlipFlop_EX3 is 
•       begin
• 1      process
• 2        begin
• 3         wait until clk'event and clk '1'
• 4           z_out lt a and b
• 5      end process                          
•      end FlipFlop_example

?? 7.12 Flip_Flop? ????
15
?3? Flip Flop? ??
? 7? ??????? ??

• 5. ??? SET??? Flip_Flop ??
• ltVHDL ??gt
•     library IEEE
•     use IEEE.std_logic_1164.all
  IEEE.numeric_std.all
•     entity FlipFlop_EX4 is
•        port (clk, set, a, b in std_logic
•             z_out out std_logic)
•     end FlipFlop_EX4
•     architecture FlipFlop_example of FlipFlop_EX4
  is 
•       begin
• 1      process (clk)
• 2        begin
• 3         if clk'event and clk '1') then
• 4            if set '1' then
• 5           z_out lt '1'
• 6           else
• 7            z_out lt a and b
• 8           end if

?? 7.13 Flip_Flop? ????
16
?3? Flip Flop? ??
? 7? ??????? ??

• 6. ???? RESET??? Flip_Flop ??
• ltVHDL ??gt
•     library IEEE
•     use IEEE.std_logic_1164.all
  IEEE.numeric_std.all
•     entity FlipFlop_EX5 is
•        port (clk, reset, preset, d in
  std_logic
•             z_out out std_logic)
•     end FlipFlop_EX5
•     architecture FlipFlop_example of FlipFlop_EX5
  is 
•       begin
• 1      process (clk, reset, preset)
• 2        begin
• 3            if reset '1' then
• 4               z_out lt '0'
• 5           elsif preset '1' then
• 6               z_out lt '1'
• 7           elsif clk'event and clk '1') then
• 8               z_out lt 'd'

?? 7.14 Flip_Flop? ????
17
?4? ???(Counter)? ??
? 7? ??????? ??

• 1. ?? ???(counter)? ??
• ltVHDL ??gt
• 1  library IEEE
• 2  use IEEE.std_logic_1164.all
• 3  use WORK.std_logic_arith.all -- VHDL
  ?????? ???? ???
• 4  entity COUNT16_EX is
• 5       port (  clk    in std_logic
• 6            count buffer std_logic_vector(3
  downto 0))  -- ??? ?? count? mode?
• 7  end COUNT16_EX                        
  -- buffer? ??
• 8  architecture COUNT_example of COUNT16_EX is
• 9    begin
• 10       process (clk)
• 11        begin
• 12         if (clk'event and clk'1') then  --
  clk? ??????
• 13           count lt count1                --
  count? 1? ?? ?

?? 7.15 (a)16? ??? (b)MUX????
18
?4? ???(Counter)? ??
? 7? ??????? ??

• 2. Load/Clear ??? ??? ??

?? 7.16 (a)Load/Clear??? ???
?? 7.16 (b) MUX? ?? ??
19
?4? ???(Counter)? ??
? 7? ??????? ??

• ltVHDL ??gt
• 1   library IEEE
• 2   use IEEE.STD_LOGIC_1164.all
• 3   use WORK.STD_LOGIC_ARITH.all
• 4   entity COUNT16_EX is
• 5      port ( clk, clear, load in std_logic
• 6             data_in in std_logic_vector(3
  downto 0)
• 7             count   buffer std_logic_vector(3
  downto 0))
• 8   end COUNT16_EX
• 9  architecture LOCL_example of COUNT16_EX is
• 10    begin
• 11      process (clk, clear)      
  -- clear? ???? ????? ??
• 12       begin
• 13         if clear'1'  then
• 14          count lt "0000"
• 15        elsif (clk'event and clk'1') then  --
  clk? ??????
• 16          if  load'1' then                
  --load? 1????
• 17          count lt data_in              
  -- count? ?? data_in? ??
• 18           else                           
  --??? ???,

20
?4? ???(Counter)? ??
? 7? ??????? ??

• 3. UP/DOWN ??? ??? ??
• ltVHDL ??gt
• 1    library IEEE
• 2    use IEEE.STD_LOGIC_1164.all use
  IEEE.STD_LOGIC_UNSIGNRD.all
• 3    entity UPDN_EX is
• 4          port ( rst,clk,updn  in std_logic
• 5               cnt     buffer
  std_logic_vector(3 downto 0))
• 6    end UPDN_EX
• 7    architecture updncount_example of UPDN_EX is
  
• 8       begin
• 9         process (rst, clk)
• 10             begin
• 11                if rst'1' then
• 12                  cnt lt (othersgt'0')
• 13                elsif rising_edge(clk) then  --
  clk? ?? ????
• 14                  if  updn'1'  then        
  -- updn1 ??,
• 15                      cnt lt cnt1        
    -- cnt? 1? ??
• 16                  else                      
  -- ??? ???, 

?? 7.17 UP/DOWN ??? ??
21
?4? ???(Counter)? ??
? 7? ??????? ??

• 4. Ring_Counter ???? ??
• ltVHDL ??gt
• 1     library IEEE
• 2     use IEEE.STD_LOGIC_1164.all use
  IEEE.STD_LOGIC_UNSIGNED.all
• 3      entity RING_COUNTER is
• 4        port (clk, reset in std_logic
• 5             count buffer std_logic_vector(7
  downto 0))
• 6      end RING_COUNTER
• 7      architecture ring_example of RING_COUNTER
  is
• 8        begin
• 9          process (clk, reset)
• 10         begin
• 11             if reset '1' then
• 12              count lt "00000001"
• 13             elsif (clk'event and clk '1')
  then
• 14                  count lt count(6 downto 0)
  count(7)
• 15             end if     
• 16        end process

?? 7.18 Ring_Counter
22
?4? ???(Counter)? ??
? 7? ??????? ??

• 5. Ripple_Counter? ??? clock ???
• ltVHDL ??gt
• 1    library IEEE
• 2    use IEEE.STD_LOGIC_1164.all
• 3    entity RIPPCOUNT_DIV16 is
• 4          port ( clock, reset in std_logic
• 5                 y out std_logic)
• 6    end RIPPCOUNT_DIV16
• 7    architecture ripplecount_ex of
  RIPPCOUNT_DIV16 is
• 8        signal DIV2, DIV4, DIV8, DIV16
  std_logic
• 9      begin
• 10         process (reset, clock)
• 11             begin
• 12                if (reset'0') then
• 13                  DIV2 lt '0'
• 14                elsif rising_edge(clock)
  then   -- clock? ?? ????
• 15                  DIV2 lt not DIV2        
  -- not DIV2? DIV? ??       

?? 7.19 16? clock ???
23
?4? ???(Counter)? ??
? 7? ??????? ??

• 19                elsif rising_edge(DIV2) then   
  -- ??? ?? DIV2? ??????
• 20                  DIV4 lt not DIV4        
  -- DIV4? ??? DIV? ??       
• 21                end if
• 22                if (reset'0') then
• 23                  DIV8 lt '0'
• 24                elsif rising_edge(DIV4) then   
  
• 25                  DIV8 lt not
  DIV8                 
• 26                end if
• 27                if (reset'0') then
• 28                  DIV16 lt '0'
• 29                elsif rising_edge(DIV8) then   
  
• 30                  DIV16 lt not
  DIV16                 
• 31                end if
• 32                if (reset'0') then
• 33                   y lt '0'
• 34                elsif rising_edge(clock)
  then   
• 35                   y lt DIV16                 
  
• 36                end if
• 37           end process

24
?5? State Machine? ??
? 7? ??????? ??

• 1. State_Machine
•    ??? ??? ??? ?? ?? ? ????? ??? ?? ?? ??
• ? ???? ??
• 2. ?? ??
• ??
  7.20 State_Machine? ?? ??
•   ? ?? ?? ??(current state logic, sequential)
•      ?? ??? ????? ???? ??? n_bit Flip_Flop? ????
• ???? ?? ??? ?? ??
•   ? ?? ?? ??(next state logic, combinational)
•      ?? ??? ???? ??? ????? ??? ???? ?????
• ??? ????? ??? ?? ??? ??? ??
•   ? ?? ??(output logic, combinational)
•      ??? ?? ??? ???? ??? ????? ??? ????
• ??? ?? ??? ??? ????? ??? ?? ??

25
?5? State Machine? ??
? 7? ??????? ??

• 3. ???? ???

?? 7.21 ??? State_Machine ??
?? 7.22 (a)???? (b)???(??7.18??)
26
?5? State Machine? ??
? 7? ??????? ??

• 4. 3_State ???? VHDL ???
• ltVHDL ??gt
•      1   library IEEE
•      2   use IEEE.STD_LOGIC_1164.all
•      3   entity STATE_MACHINE is
•      4      port (Clock, Reset, SlowRAM in
  std_logic
•      5           Read, Write out std_logic)
•      6   end STATE_MACHINE
•      7   architecture 3state_EX of STATE_MACHINE
  is
•      8    type StateType is (ST_Read, ST_Write,
  ST_Delay)--???? ??  
•      9    signal CurrentState, NextState
  StateType   --????,?????
•     10   begin
  -- signal? ??
• 11     Sequntial process          
•     12      begin
•     13       wait until rising_edge(Clock)

?? 7.23 3_State ???
27
?5? State Machine? ??
? 7? ??????? ??

• 14        if (reset '1') then          
  -- reset 1??,
•    15          CurrentState lt ST_Read    --
  ????? ST_Read? ????,
•    16        else
•    17          CurrentState lt NextState  --
  ????? ????? ??
•    18        end if
•    19      end process Sequential
•    20  Combi process (CurrentState)   -- ????
  ??? process?
•    21    begin     
•    22     case CurrentStates is        
  -- CurrentState? ?? ???
•    23       when ST_Read gt        --
  CurrentState? ?? ST_Read??
•    24                Read lt '1'         
  -- Read? 1? ????,
•    25                 Write lt '0'        
  -- Write? 0? ????,
•   26                  NextState lt ST_Write --
  NextState? ST_Write? ??
•    27       when ST_Write gt
•    28                Read lt '0'
•    29                Write lt '1'
•    30                if (SlowRAM '1') then
•    31                   NextState lt ST_Delay
•    32                else

?? 7.23 3_State ???
28
?5? State Machine? ??
? 7? ??????? ??

• 36       when ST_Delay gt
•    37                Read lt '0'
•    38                 Write lt '0'
•    39                  NextState lt ST_Read
•    40       when others gt
•    41                Read lt '0'
•    42                 Write lt '0'
•    43                  NextState lt ST_Read
•    44         end case
•    45        end process Combi              
•    46      end 3state_EX 

?? 7.23 3_State ???
29
?5? State Machine? ??
? 7? ??????? ??

• 4. 4_state ???? VHDL ???
• ltVHDL ??gt
•     1   library IEEE
•     2   use IEEE.STD_LOGIC_1164.all
•     3   entity STATE_MACHINE is
•     4      port (clk, reset in std_logic
•     5           input in std_logic_vector(1
  downto 0)
•     6           output out std_logic_vector(1
  downto 0))
•     7   end STATE_MACHINE
•     8   architecture state_EX of STATE_MACHINE is
  
•     9     type states is (s0, s1, s2,
  s3)            -- states? ????? ??  
•    10     signal present_state, next_state
  states -- ????, ?????
•    11    begin signal? ??

?? 7.24 4_State Machine? ???
30
?5? State Machine? ??
? 7? ??????? ??

• 12     sequntial process (reset, clk)  --
  register? ???? process?
•    13      begin
•    14       if reset '1' then          
  -- reset 1??,
•    15         present_state lt s0       
  -- ????? s0? ????,
•    16       elsif rising_edge(clk) then    --
  ??? ?? clk? ??????
•    17         present_state lt next_state --
  ????? ????? ??
•    18       end if
•    19      end process sequential
•    20   combi process (present_state, inputs)  
  -- ???? ??? process?
•    21    begin     
•    22     case present_states is
•    23       when s0 gt output lt "00" -- ?????
  s0? ?, ??? 00? ????,
•    24         if inputs "11" then       --
  ??? 11??,
•    25           next_state lt s0         --
  ??? ??? ??
•    26         else
•    27           next_state lt s1        --
  ??? 11? ???, ????? s1
•    28         end if
• 29       when s1 gt output lt "01" -- ?? ???
  s1??, ??? 01
•    30         if inputs "11" then        --
  ??? 11??,

?? 7.24 4_State Machine? ???
31
?5? State Machine? ??
? 7? ??????? ??

• 35        when s2 gt output lt "10"  -- ???
  ??? s2??, ??? 10      
•    36          if input "11" then    -- ???
  11??,
•    37           next_state lt s2      -- ??? ???
  ????,
•    38          else                     --
  ??? ???,
•    39           next_state lt s3      -- ?? ???
  s3
•    40         end if
•    41         when s3 gt output lt "11"  -- ???
  ??? s3??, ??? 11      
•    42          if input "11" then     -- ???
  11??,
•    43           next_state lt s3      -- ??? ???
  ????,
•    44          else                     --
  ??? ???,
•    45           next_state lt s0      -- ?? ???
  s0
•    46          end if      
•    47       end case
•    48      end process combi
•    49    end state_EX

?? 7.24 4_State Machine? ???
32
?5? State Machine? ??
? 7? ??????? ??

• 5. ?? ??(Moore Machine)? ?? ??(Mealy Machine)
•   ? ?? ??
•     ????? ?? ????? ???? ???? ? ?? ????
• ??? ??? ??
•   ? ?? ??
•     ????? ????? ??? ??? ??? ????, ?????
• ??? ?? ????? ?? ?? ? ? ??    
•   ? ??

?? 7.25 (a) Moore Machine (b) Mealy Machine? ??
33
?5? State Machine? ??
? 7? ??????? ??

• ?Moore_Machine? VHDL ??
• ltVHDL ??gt
•     1   library IEEE
•     2   use IEEE.STD_LOGIC_1164.all
•     3   entity Moore_STATE is
•     4      port (clk, reset, Red, Green, Blue
  in std_logic
•     5           NewColor out std_logic)
•     6   end Moore_STATE

?? 7.26 Moore_Machine? ???
34
?5? State Machine? ??
? 7? ??????? ??

• 7   architecture Moore_EX of Moore_STATE is
•     8     type Color is (RedState, GreenState,
  BlueState, WhiteState)   
•     9     signal PresentState, NextState
  Color  
•    10    begin
•    11     sequntial process (reset, clk)     --
  register? ???? process?
•    12      begin
•    13       if reset '1' then          
  -- reset 1??,
•    14         PresentState lt WhiteState   --
  ????? WhiteState? ????,
•    15       elsif rising_edge(clk) then   
  -- ??? ?? clk? ??????
•    16         PresentState lt NextState  --
  ????? ????? ??
•    17       end if
•    18      end process sequential
•    19   combi process (PresentState, Red,
  Green, Blue)   -- ???? ??? process?    

?? 7.26 Moore_Machine? ???
35
?5? State Machine? ??
? 7? ??????? ??

• 20    begin     
•    21    case PresentStates is
•    22     when RedState gt NewColor lt '1'
  --????? RedState? ?, ??? 1
•    23        if Red '1' then                  
  -- Red? 1??,
•    24          NextState lt RedState     -- ???
  ??? ??
•    25        else
•    26          NextState lt WhiteState  --
  ????? WhiteState
•    27        end if
•    28      when GreenState gt NewColor lt '1'
  --?? ??? GreenState??, ??? 1
•    29         if Green '1' then       
  -- ?? Green? 1??,
•    30           NextState lt GreenState   -- ???
  ??? ????,
•    31         else                      
  -- ??? ???,
•    32           NextState lt WhiteState    --
  ????? WhiteState
•    33         end if
•    34   when BlueState gt NewColor lt '1'  --
  ??? ??? BlueState??, ??? 1  
•    35      if Blue '1' then        
  -- ??? 1??,
•    36        NextState lt BlueState        --
  ??? ??? ????,
•    37      else                    
  -- ??? ???,
•    38        NextState lt WhiteState      -- ??
  ??? WhiteState

?? 7.26 Moore_Machine? ???
36
?5? State Machine? ??
? 7? ??????? ??

• 40   when WhiteState gt NewColor lt '0' --
  ????? WhiteState??,???0      
•    41      if Red '1' then        
  -- ??? 1 ??,
•    42        NextState lt RedState         
  -- ??? ??? ????,
•    43      elsif Green '1' then            
  -- ??? ??, Green '1'??,
•    44        NextState lt GreenState       
  -- ?? ??? GreenState
•    45      elsif Blue '1' then                  
  -- ??? ??, Blue '1'??,
•    46        NextState lt BlueState       
  -- ?? ??? GreenState
•    47      else
•    48        NextState lt WhiteState       
  -- ??? ??     
•    49      end if      
•    50   when others gt NewColor lt '0' 
•    51          NextState lt WhiteState 
•    52   end case
•    53  end process combi
•    54 end Moore_EX

?? 7.26 Moore_Machine? ???