AES Acceleration Via FPGA Co-Processor

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AES Acceleration ViaFPGA Co-Processor

• Adam Jackson
• Daniel Risse
• Iowa State University
• CprE 583 Fall 2009

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AES Acceleration ViaFPGA Co-Processor

• Team Members Responsibilities
• Adam Jackson
• Primary hardware AES implementation
• Coprocessor Interfacing
• Daniel Risse (project leader)
• Linux installation on PPC440 on FPGA
• Software configuration/building
• Documentation and reporting duties shared

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AES Acceleration Via FPGA Co-Processor

• Motivation
• AES can be greatly accelerated in hardware
• Possible parallelism
• Multiple tools can benefit from accelerated AES
• Goal
• AES coprocessor
• Linux running on ml507 board
• Accelerated instruction integration

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System Block Diagram
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Milestones

• 128-bit data/key AES
• Linux running on ml507 board
• Accelerated instruction integration
• Complete Paper and Presentation Slides
• Submit Final Paper
• Final Presentation/Demo

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Concerns/Risks

• Implementation
• AES data width greater than APU bus width
• Difficulty of installing/running Linux kernel on
  PPC
• Difficulty of configuration and cross-compilation
• Difficulty of integrating accelerated
  instructions into existing software
• Conceptual
• AES Algorithm
• Cross-compilation
• Open-source code modification

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AES Acceleration Unit

• 128-bit case
• Data to encrypt is 4x4 matrix of bytes
• Iterate through rounds
• Substitute each byte
• Lookup-table of S-boxes
• Rotate-shift bytes within each row
• Mix Columns
• XOR each byte with round-key
• Round keys derived from key-schedule algorithm
• Final Round
• Same as other rounds, but omits column-mixing
• Decryption is the inverse algorithm using the
  same key

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Encryption Round Block Diagram
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Encryption Unit Block Diagram
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Encrypt FSM
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Decryption Round Block Diagram
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Decryption Unit Block Diagram
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Decrypt FSM
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AES Coprocessor FSM
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Linux Build Process

• Clone git trees from Xilinx
• Setup build environment (assumes ELDK)
• Configure and make Linux kernel image
• Load hardware BIT file onto FPGA
• Use XMD to connect to PPC and upload ELF file,
  run
• Cross-compile custom software on host machine
  with statically-linked libraries
• Upload to Linux on PPC via FTP
• Can interact with Linux on PPC via minicom or
  telnet

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Future Possibilities

• Integrate accelerated AES into other applications
  like SCP/SFTP, SSH, SSL/TLS
• Integrate software into Linux image build
  (persistence)

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References

• 1 Xilinx, Embedded Processor Block in Virtex-5
  FPGAs, Reference Guide, Jan. 20, 2009, Online
  Available http//www.xilinx.com/support/documenta
  tion/user guides/ug200.pdf
• 2 National Institutue of Standards and
  Technology, Federal Information Processing
  Standard 197, Announcing the AES ENCRYPTION
  STANDARD, Available http//csrc.nist.gov/publica
  tions/?ps/?ps197/?ps-197.pdf
• 3 W. Stallings, Cryptography and Network
  Security, Upper Saddle River, NJ Prentice Hall,
  2003, pp. 133, 139-171.
• 4 Con?guring, Building and Loading PowerPC
  Linux, Oct. 6, 2009. Online Available
  http//xilinx.wikidot.com/powerpc-linux
  Accessed Dec. 9, 2009
• 5 Wikipedia, Advanced Encryption Standard,
  Dec. 8, 2009. Online Available
  http//en.wikipedia.org/wiki/Advanced Encryption
  Standard Accessed Oct. 22, 2009

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AES Acceleration Via FPGA Co-Processor

• Questions?