Semiconductor Memories

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CHAPTER 6
Semiconductor Memories
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CLASSIFICATION OF SEMICONDUCTOR MEMORIES
Semiconductor memories
volatile
Non-volatile
SRAM, DRAM
ROM, EPROM
loose their data once the power supply is turned
off.
can retain their data even after power is
removed.
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Access parameters

• Read-access time
• Propagation delay from the time when the address
  is presented at the chip to the time data is
  available at the output.
• Cycle time
• Minimum time between initiation of a read
  operation and the initiation of another operation.

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SRAM

• SRAM
• a static memory.
• it is bistable.
• two inverters continuously maintain the value of
  the bit, as long as power is on.
• 6 transistors are required to store 1 bit (or 4
  transistors 2 registers).

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SRAM

• High-speed
• Low capacity
• Expensive
• Large chip area.
• Continuous power use to maintain storage

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SRAM

• Single cell stores single bit.
• 4T2R design (old)
• 6T design

6T design
4T2R design (old)
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SRAM
Two SRAM cells dominate CMOS industry 6T Cell
all CMOS transistors better noise immunity 4T
Cell 2R replaces pMOS with high resistance
(1G?) resistors slightly smaller than 6T
cell requires an extra high-resistance process
layer
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SRAM
4T2R

• Word line
• Asserted connects to complementary bit lines.

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6T Cell Design Challenge

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SRAM Cell Layout
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SRAM

• Resistor-Transistor pair divide voltage between
  Vcc and GND
• T2 high resistance
• A close to VCC
• T2 low resistance
• A close to Gnd.

A
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SRAM

• T2 high impedance
• A close to VCC
• T3 enabled
• T3 low impedance
• B close to Gnd
• T2 low impedance
• A close to Gnd.
• T3 disabled
• T3 high impedance
• B close to VCC

A
B
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SRAM

• Two stable states.
• Asserted word line sends complimentary values to
  the two bit lines.
• This is the stored bit.
• Bitline 0 contains bit
• Bitline 1 contains inverse of bit

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SRAM

• There is always a current through one of the
  transistor-resistor pairs.
• Use transistors instead of resistors to save
  energy.
• However, transistors can use up more space.

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SRAM (6 T)

• Cell consists of two lines of transistors,
  dividing the voltage between VCC and GND
• Cross-coupled.
• T2 in high impedance ?T5 in low impedance
• T2 in low impedance ? T5 in high impedance

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SRAM (6 T)

• Assume T2 high impedance, T5 low impedance.
• Point A VCC
• T3 in low impedance and T6 in high impedance
• Point B GND
• T2 in high impedance, T5 low impedance.
• Stable State

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SRAM (6 T)

• Assume T2 low impedance, T5 high impedance.
• Point A GND
• T3 in high impedance and T6 in low impedance
• Point B GND
• T2 in low impedance, T5 high impedance.
• Stable State

A
B
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SRAM (6 T)

• 6T cell is in two stable states.
• If the word line is asserted, complementary
  values are placed on the two bit lines.

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DRAM

• Dynamic Random Access Memory
• Dynamic
• Periodically refresh information in a bit cell.
• Else it is lost.
• Small footprint transistor capacitor
• High density memory
• Cheap.
• Read complicated
• Slower than SRAM

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DRAM

• DRAM
• a dynamic memory
• the bit is stored by internal capacitance and
  dissipates (leaks) over time
• it is also destroyed on a read operation and
  therefore required periodic refreshment.
• 1 transistor (with capacitance) is required to
  store 1 bit.

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DRAM

• First introduced (with a 3T cell) by Intel in
  1970.
• 1kb capacity.
• Classic 1T cell introduced in 1973.
• 4kb capacity.

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DRAM

• DRAM cell
• Capacitor
• Transistor

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DRAM

• To write a 0
• Turn bit-line voltage to 0V.
• Turn word-line voltage to VCC.
• Turns access transistor on.
• Empties charge from capacitor.
• Turn word-line voltage back to 0V.

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DRAM

• To write a 1
• Turn bit-line voltage to VCC.
• Turn word-line voltage to VCC.
• Turns access transistor on.
• Charges capacitor.
• Turn word-line voltage back to 0V.

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Flash Memory
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Floating Gate Fundamentals

• Floating Gate between control gate and channel in
  MOSFET.
• Not directly connected to an outside line.

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Floating Gate Fundamentals

• First used in Erasable Programmable Read Only
  Memory (EPROM)

• To function, Floating Gate EPROM cell needs to be
  able to maintain a charge on the floating gate.
• Charge completely isolated, hence can be stored
  for long times.

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Floating Gate Fundamentals

• No charge in floating gate.
• Assume control gate, source, drain at GND.
• Increase voltage in control gate
• Floating gate voltage also increases, but at a
  lower rate.
• Raises the threshold value of the transistor.
• When threshold voltage is high enough, creates a
  channel between source and drain.
• Threshold value about twice as high.

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Floating Gate Fundamentals

• Floating gate (negatively) charged
• Isolates control gate from forming a channel at
  normal threshold values.

• Discharging the floating gate
• Exposure to UV light for twenty minutes.
• Chips have a crystal cover that allows UV light
  to hit the chip.
• UV light charges electrons on the floating gate
  so that they can break through the isolation
  layer around the floating gate.

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Floating Gate Fundamentals

• To charge the floating gate
• Apply 12V (or higher) to control and drain
• Maintain source and substrate at ground
• For a few hundred microseconds.
• Creates a large drain current.
• Accelerates electrons to high velocity hot
  electrons.
• Break through the silicon substrate SiO2 barrier.
• Some get caught in the floating gate.
• Floating gate charge causes channel inversion.
• Electrons remain trapped on floating gate.
• Potential about -5V.

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Floating Gate Fundamentals

• Need to avoid trapping electrons in SiO2 after
  several charge / discharge cycles.
• Could raise threshold value of transistor.
• Careful growth of SiO2 layer.