Seminar

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http//edu.idec.or.kr
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• VCR
• LP?
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• TV
• ???
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• AM, FM
• ???

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• DVR
• CD
• MP3
• ??? TV
• ??? ???
• ??? ???
• DAB
• ???

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Media Convergence
????/???/DSC
VOD / MP3
WLAN/UWB ??
3D Game
PC
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Source SIEMENS
Personal G/W
Navigator
Health
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• Carrier
• Message Signal
• Amplitude-Modulated Signal
• Frequency-Modulated Signal

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Channel Coding
Modulation
Multiple Access
Source Coding
Channel Decoding
Demodulation
Multiple Access
Source Decoding
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Source and Channel Coding
channel
source coding
channel decoding
source decoding
channel coding
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Channel Coding Error Detection

• Parity Check
• Even parity
• 01010 ? 001010
• Odd parity
• 01010 ? 101010

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Channel Coding Error Correction - 1

• (3,1) code
• 0 ? 000
• 1 ? 111
• If 010 is received,
• decision 0
• If 011 is received,
• decision 1

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Channel Coding Error Correction - 2

• (5,2) code
• 00 ? 00000
• 01 ? 01011
• 10 ? 10101
• 11 ? 11110
• If 01000 is received,
• decision 00
• If 01010 is received,
• decision 01

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Digital Modulation
Phase Shift Keying
Frequency Shift Keying
Amplitude Shift Keying
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Amplitude Shift Keying

• Transmitter

Baseband signal Am
Bandpass signal Am cos2?fct
Carrier cos2?fct
Receiver
Decision
cos2?fct
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Multiple Access

• Multiple Access
• Sharing of medium by many users
• Purpose
• ??? ?? ??? ?? ???? ???? ??
• communication resource? ????? ???? ??
• FDMA(Frequency Division Multiple Access)? ??
• ?? ?? ??? ????? FDMA

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Frequency-Division Multiple Access
user 4
Guard band
Frequency
user 3
Guard band
user 2
Guard band
user 1
Time
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Time-Division Multiple Access
Frequency
user 1
user 2
user 1
user 2
Guard time
Guard time
Guard time
Guard band
Time
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Code-Division Multiple Access

• Direct Sequence CDMA

user 1, 2, 3, 4
Frequency
Time
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Applications Beat Moores Law
Battery Capacity
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Handphone Hardware
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CDMA ??? ?? - 1
LCD Application S/W UI
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RF
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PLL
Baseband Analog Processor ???? ????
Modem Processor ????? Digital? ?? ?? SOFTWARE?
?? ???? ?? ??? ???? ????
??
?? S/W (Layer 1,2,3)
Battery
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CDMA ??? ?? - 2
Mobile Station Modem
LCD
Base- Band Analog
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Duplexer
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SOC(System On a Chip)
1995?
2003?
CPU
DSP
CPU
DSP
Mem
Logic
System
Memory
Logic

• 0.5?m
• 20? gate
• ?? VLSI

• 0.13?m
• 1000? gate
• System? 1 chip?

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???? SOC? ??

• 1M gates
• Intellectual Property (IP)
• H/W S/W Codesign
• System Level Verification Tools
• Deep Submicron Technology
• Mixture of Blocks
• Microprocessor
• DSP
• Embeded Memory
• I/O Bus interface
• User defined ASIC Logic

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SOC?? CDMA ??
Product SCOM3000, CDMA modem
processor Die Size 76 x 8 ? ( 035um ) 2MB
Protocol Stack Software ARM RISC OAK
DSP 8K/13K QCELPS Speech Coders 8K EVRC Speech
Code 16msec Acoustic Echo Canceller DFM (AMPS)
Firmware Speech Recognition
SCRATCH SRAM
CDMA AMPS MODEM
DSP PROCESSOR
DSP PGM ROM
DSP DATA SRAM
OAK Peri
Viterbi Decoder
DATA ROM
ARM CPU
ARM Peri
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Typical Wireless System Using SOC
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FPGA
Algorithm ??
?? ASIC (ES,CS)
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?? S/W (Layer 1,2,3 S/W)

• ???
• RF
• HW
• ?? SW

• RF
• HW
• Simple UI
• ????
• ???

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HW/SW Codesign Coverification
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Top-down Design Concept
Architecture Design
Performance Optimization
Synthesized Netlist
Netlist with Test
Optimized Netlist
RTL Spec
RTL Gate Design
Optimizations
Refinements/ ECOs
Spec Iterations
Test Insertion Clk Tree Insertion
Physical Design
Physical Optimization
Place Route
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SoC Design Methodology
Issues
Methodology
Spec.
Design
Verification
Behavioral Design
System-level design
SOC Verification
Architectural Design
IP Reuse
DFT and Test
SOC Issue
RTL to GDS
RTL Design
SW Design
Signal Design Integrity
VDSM Issue
Chip Imple- mentation
System Integration
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Challenges in Very Deep-Submicron Design

• VDSM
• Higher resistance
• Higher cross-coupling
• Non-linear timing
• IR drop
• Electromigration
• Inductance
• Capcitance

• SOC
• Time-to-market
• Larger die, larger database
• Larger design space
• Long wires, more density
• Higher clock speeds
• Reuse, IPs

Require detailedanalysis to understand physical
interactions
Need abstraction levels to manage complexity
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Design Tradeoff (Performance vs. Flexibility)
Performance (Speed Power Cost)
ASIC/ASSP SoC
Goal
SoC platform
Programmable (uP, DSP or FPGA)
Flexibility Time to Market
Source DesignCon2001 (Chameleon)
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The Energy-Flexibility Gap
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SoC Technology
Architecture

• Software Defined Radion (SDR)
• Reconfigurable Microprocessor
• Network on a Chip

Low Power

• Dynamic Voltage Scaling
• Non-Volatile Logic

Silicon Process
Design Methodology

• System in Package (SIP)
• MEMS
• Nanotechnology

• Platform-based Design
• Reusable Ips
• HW/SW Codesign and
• Coverification

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CPU
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DSP

• CPU vs. DSP
• CPU
• ??
• DSP (Digital Signal Processor)
• Digital Signal Processing ??? ???? ???? ??
• Characteristics of DSP algorithms
• Computation-intensive
• Multiplication-intensive
• Special computation
• Data intensive
• Large amount of data
• No locality in data (Cache is not very useful)
• Iterative
• For-loop
• Real-time

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Bluetooth
Wireless LAN (WiFi)
Wireless MAN
ZigBee
????? (WiBro)
UWB
WiMax
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Ubiquitous Seamless Service
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SoC Crisis
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• SOC ???? ???? ???? ??? ??
• ?? VLSI? ??? ???? ???, ????, ????,

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????

• S. Haykin, "Communication Systems", John Wiley
  Sons, 4th edition, 2001
• Chapter 2 Continuous-Wave Modulation
• Chapter 6 Passband Digital Transmission
• Chapter 7 Spread Spectrum Modulation
• Chapter 10 Error Control Coding
• B. Sklar, "Digital Communications Fundamentals
  and Applications", Prentice Hall, 2001
• Chapter 1 Signals and Spectra
• Chapter 4 Bandpass Modulation and Demodulation
• www.ieee802.org

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